KEYMGR Simulation Results

Thursday July 04 2024 23:02:28 UTC

GitHub Revision: 3e678c112b

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 94940390549829454688103081328166376218078465228811124044523808815554354133843

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	32.920s	5.692ms	50	50	100.00
V1	random	keymgr_random	31.010s	1.857ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.430s	138.486us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.540s	25.264us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	31.640s	2.660ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	9.540s	1.494ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.400s	253.484us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.540s	25.264us	20	20	100.00
		keymgr_csr_aliasing	9.540s	1.494ms	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	1.847m	1.996ms	50	50	100.00
V2	sideload	keymgr_sideload	1.385m	9.877ms	50	50	100.00
		keymgr_sideload_kmac	29.440s	1.356ms	50	50	100.00
		keymgr_sideload_aes	48.060s	5.822ms	50	50	100.00
		keymgr_sideload_otbn	1.185m	13.953ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	47.350s	2.773ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	7.650s	169.690us	50	50	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	10.070s	2.890ms	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	1.025m	6.330ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	46.480s	19.899ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	18.430s	3.147ms	50	50	100.00
V2	stress_all	keymgr_stress_all	6.538m	70.475ms	49	50	98.00
V2	intr_test	keymgr_intr_test	0.970s	79.397us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.130s	26.945us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	4.490s	124.480us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	4.490s	124.480us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.430s	138.486us	5	5	100.00
		keymgr_csr_rw	1.540s	25.264us	20	20	100.00
		keymgr_csr_aliasing	9.540s	1.494ms	5	5	100.00
		keymgr_same_csr_outstanding	4.000s	1.166ms	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.430s	138.486us	5	5	100.00
		keymgr_csr_rw	1.540s	25.264us	20	20	100.00
		keymgr_csr_aliasing	9.540s	1.494ms	5	5	100.00
		keymgr_same_csr_outstanding	4.000s	1.166ms	20	20	100.00
V2		TOTAL			739	740	99.86
V2S	sec_cm_additional_check	keymgr_sec_cm	17.050s	1.948ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	17.050s	1.948ms	5	5	100.00
		keymgr_tl_intg_err	11.150s	293.543us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	5.630s	418.678us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	5.630s	418.678us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	5.630s	418.678us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	5.630s	418.678us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	16.770s	533.384us	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	17.050s	1.948ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	17.050s	1.948ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	11.150s	293.543us	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	5.630s	418.678us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.847m	1.996ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	31.010s	1.857ms	50	50	100.00
		keymgr_csr_rw	1.540s	25.264us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	31.010s	1.857ms	50	50	100.00
		keymgr_csr_rw	1.540s	25.264us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	31.010s	1.857ms	50	50	100.00
		keymgr_csr_rw	1.540s	25.264us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	7.650s	169.690us	50	50	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	46.480s	19.899ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	46.480s	19.899ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	31.010s	1.857ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	30.020s	4.804ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	17.050s	1.948ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	17.050s	1.948ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	17.050s	1.948ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	33.620s	4.861ms	49	50	98.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	7.650s	169.690us	50	50	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	17.050s	1.948ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	17.050s	1.948ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	17.050s	1.948ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	33.620s	4.861ms	49	50	98.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	33.620s	4.861ms	49	50	98.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	17.050s	1.948ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	33.620s	4.861ms	49	50	98.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	17.050s	1.948ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	33.620s	4.861ms	49	50	98.00
V2S		TOTAL			164	165	99.39
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	26.030s	646.869us	31	50	62.00
V3		TOTAL			31	50	62.00
		TOTAL			1089	1110	98.11

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	16	16	15	93.75
V2S	6	6	5	83.33
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.71	99.04	98.11	98.24	100.00	99.02	98.41	91.19

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:825) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 18 failures:

  • Test keymgr_stress_all_with_rand_reset has 18 failures.

    • 3.keymgr_stress_all_with_rand_reset.11948729851358384734050868033323824110813392184099516971295056503421294663593
      Line 467, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/3.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 112379671 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10008 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 112379671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 5.keymgr_stress_all_with_rand_reset.99079793983953646254734845185764335331216310636555306008788454364376249043061
      Line 330, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/5.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 506079908 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 506079908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 16 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 1 failures:

  • Test keymgr_stress_all has 1 failures.

    • 23.keymgr_stress_all.73193547689649022553871084139616080133959586627738517262765338751199010566640
      Line 1196, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/23.keymgr_stress_all/latest/run.log

        UVM_ERROR @ 461363032 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
        UVM_INFO @ 461363032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:749) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test keymgr_stress_all_with_rand_reset has 1 failures.

    • 36.keymgr_stress_all_with_rand_reset.28970330377159313419792151701491349495650450596960623316209973478000314747265
      Line 555, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/36.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 123070361 ps: (cip_base_vseq.sv:749) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 123070361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (keymgr_custom_cm_vseq.sv:45) [keymgr_custom_cm_vseq] wait timeout occurred! has 1 failures:

  • Test keymgr_custom_cm has 1 failures.

    • 48.keymgr_custom_cm.85622978066031073954675942974547039714020432156499625198649995733524503742222
      Line 308, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/48.keymgr_custom_cm/latest/run.log

        UVM_FATAL @ 10608286651 ps: (keymgr_custom_cm_vseq.sv:45) [uvm_test_top.env.virtual_sequencer.keymgr_custom_cm_vseq] wait timeout occurred!
        UVM_INFO @ 10608286651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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