KEYMGR Simulation Results

Friday July 05 2024 23:02:55 UTC

GitHub Revision: `9edf84e236`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 47623749544922802985321435118963335754001495105472137721881337469861493653463

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	34.950s	12.089ms	50	50	100.00
V1	random	keymgr_random	1.284m	7.199ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.480s	38.560us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.490s	117.862us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	17.470s	1.339ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	9.710s	560.805us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.180s	196.597us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.490s	117.862us	20	20	100.00
		keymgr_csr_aliasing	9.710s	560.805us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	1.727m	7.362ms	49	50	98.00
V2	sideload	keymgr_sideload	36.280s	3.185ms	50	50	100.00
		keymgr_sideload_kmac	26.460s	9.347ms	50	50	100.00
		keymgr_sideload_aes	19.630s	859.656us	50	50	100.00
		keymgr_sideload_otbn	1.420m	22.365ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	37.130s	8.268ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	16.050s	1.132ms	50	50	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	6.310s	605.525us	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	51.200s	8.612ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	1.444m	9.859ms	48	50	96.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	25.130s	2.234ms	50	50	100.00
V2	stress_all	keymgr_stress_all	3.468m	10.173ms	46	50	92.00
V2	intr_test	keymgr_intr_test	0.910s	24.826us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.150s	99.048us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	4.490s	136.003us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	4.490s	136.003us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.480s	38.560us	5	5	100.00
		keymgr_csr_rw	1.490s	117.862us	20	20	100.00
		keymgr_csr_aliasing	9.710s	560.805us	5	5	100.00
		keymgr_same_csr_outstanding	4.030s	218.915us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.480s	38.560us	5	5	100.00
		keymgr_csr_rw	1.490s	117.862us	20	20	100.00
		keymgr_csr_aliasing	9.710s	560.805us	5	5	100.00
		keymgr_same_csr_outstanding	4.030s	218.915us	20	20	100.00
V2		TOTAL			733	740	99.05
V2S	sec_cm_additional_check	keymgr_sec_cm	18.980s	1.119ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	18.980s	1.119ms	5	5	100.00
		keymgr_tl_intg_err	11.170s	1.612ms	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	3.810s	127.658us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	3.810s	127.658us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	3.810s	127.658us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	3.810s	127.658us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	13.870s	2.316ms	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	18.980s	1.119ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	18.980s	1.119ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	11.170s	1.612ms	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	3.810s	127.658us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.727m	7.362ms	49	50	98.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	1.284m	7.199ms	50	50	100.00
		keymgr_csr_rw	1.490s	117.862us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	1.284m	7.199ms	50	50	100.00
		keymgr_csr_rw	1.490s	117.862us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	1.284m	7.199ms	50	50	100.00
		keymgr_csr_rw	1.490s	117.862us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	16.050s	1.132ms	50	50	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	1.444m	9.859ms	48	50	96.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	1.444m	9.859ms	48	50	96.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	1.284m	7.199ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	14.460s	756.956us	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	18.980s	1.119ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	18.980s	1.119ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	18.980s	1.119ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	29.760s	977.745us	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	16.050s	1.132ms	50	50	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	18.980s	1.119ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	18.980s	1.119ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	18.980s	1.119ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	29.760s	977.745us	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	29.760s	977.745us	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	18.980s	1.119ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	29.760s	977.745us	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	18.980s	1.119ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	29.760s	977.745us	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	27.460s	2.287ms	28	50	56.00
V3		TOTAL			28	50	56.00
		TOTAL			1081	1110	97.39

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	16	16	13	81.25
V2S	6	6	6	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.73	99.04	98.15	98.37	100.00	99.02	98.41	91.17

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 21 failures:
- Test keymgr_stress_all_with_rand_reset has 21 failures.
  - 4.keymgr_stress_all_with_rand_reset.46596710131731669181389704672071736943576450705859965700380402065812734212165
    Line 270, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/4.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 426309964 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 426309964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 11.keymgr_stress_all_with_rand_reset.22382411996495467636876580591554408216915038758091249643797654514275971354110
    Line 571, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/11.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 204369071 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 204369071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 19 more failures.
UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 3 failures:
- Test keymgr_cfg_regwen has 1 failures.
  - 17.keymgr_cfg_regwen.46100240549988269279347645431475044459426001108225448980533190310838128435128
    Line 386, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/17.keymgr_cfg_regwen/latest/run.log
```
  UVM_ERROR @  15784658 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @  15784658 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test keymgr_stress_all has 1 failures.
  - 21.keymgr_stress_all.29910974464417923867372197546441180011164566779226826369733412914217575164296
    Line 2431, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/21.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 1249731626 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @ 1249731626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test keymgr_hwsw_invalid_input has 1 failures.
  - 27.keymgr_hwsw_invalid_input.7289079162702190439170693461593984298601144937505424947840738781112685117965
    Line 407, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/27.keymgr_hwsw_invalid_input/latest/run.log
```
  UVM_ERROR @  11609512 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @  11609512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:651) [scoreboard] Check failed act_state == addr_phase_working_state (* [*] vs * [*]) has 1 failures:
- Test keymgr_stress_all has 1 failures.
  - 3.keymgr_stress_all.101492641282428929023058989740033816852352170390315614947410809503037789020915
    Line 730, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/3.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 415801540 ps: (keymgr_scoreboard.sv:651) [uvm_test_top.env.scoreboard] Check failed act_state == addr_phase_working_state (5 [0x5] vs 6 [0x6])
  UVM_INFO @ 415801540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) AES key at state StOwnerIntKey for Sealing Aes has 1 failures:

Test keymgr_stress_all has 1 failures.

16.keymgr_stress_all.35013611463697006375975982224499389171924433422155533590912082876062144277760
Line 1768, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/16.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 1924797335 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (6709557448868251437594965686890880916510134726600666455672005319547682867204505671669242643444804285572239126425066079268406848731614883292751136155170979 [0x801ba23720510c10d78a2a434c40d601e5968025f22e6582f8247a29a56b8b35d09cfb7173ba57e1c08e8607be519d819db8dc01d3b641b37b71410e82caf8a3] vs 6709557448868251437594965686890880916510134726600666455672005319547682867204505671669242643444804285572239126425066079268406848731614883292751136155170979 [0x801ba23720510c10d78a2a434c40d601e5968025f22e6582f8247a29a56b8b35d09cfb7173ba57e1c08e8607be519d819db8dc01d3b641b37b71410e82caf8a3]) AES key at state StOwnerIntKey for Sealing Aes
  UVM_INFO @ 1924797335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_operation_err triggered unexpectedly has 1 failures:
- Test keymgr_hwsw_invalid_input has 1 failures.
  - 22.keymgr_hwsw_invalid_input.105805592878725337432241467060166066677411393431688085573235752994220172624166
    Line 520, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/22.keymgr_hwsw_invalid_input/latest/run.log
```
  UVM_ERROR @  19311970 ps: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_operation_err triggered unexpectedly
  UVM_INFO @  19311970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data !=gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share0_output_*` has 1 failures:
- Test keymgr_stress_all has 1 failures.
  - 25.keymgr_stress_all.21041009039680464274037259977419182481822881785076278031836838753375624614406
    Line 2420, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/25.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 1008344821 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (2287788465 [0x885ce1b1] vs 2287788465 [0x885ce1b1]) reg name: keymgr_reg_block.sw_share0_output_1
  UVM_INFO @ 1008344821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:749) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 42.keymgr_stress_all_with_rand_reset.20582097542084510821819816879601785365937152487542929733547086497930986388992
    Line 314, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/42.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 448465269 ps: (cip_base_vseq.sv:749) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 448465269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```