KEYMGR Simulation Results

Saturday July 06 2024 23:02:28 UTC

GitHub Revision: `c42c47ec2d`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 3200059823452722292543998130245428086525417237473114929151723951411399280153

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	24.230s	1.416ms	50	50	100.00
V1	random	keymgr_random	1.264m	2.432ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.160s	36.055us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.470s	26.510us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	14.660s	257.505us	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	7.870s	1.386ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.330s	143.885us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.470s	26.510us	20	20	100.00
		keymgr_csr_aliasing	7.870s	1.386ms	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	1.351m	3.605ms	50	50	100.00
V2	sideload	keymgr_sideload	34.650s	5.413ms	50	50	100.00
		keymgr_sideload_kmac	31.000s	1.264ms	50	50	100.00
		keymgr_sideload_aes	1.008m	1.796ms	48	50	96.00
		keymgr_sideload_otbn	46.740s	7.172ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	23.650s	1.828ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	19.180s	1.508ms	49	50	98.00
V2	kmac_error_response	keymgr_kmac_rsp_err	6.470s	794.194us	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	1.179m	1.967ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	56.280s	8.242ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	12.260s	1.702ms	50	50	100.00
V2	stress_all	keymgr_stress_all	10.124m	59.335ms	49	50	98.00
V2	intr_test	keymgr_intr_test	0.960s	19.705us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.090s	31.850us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	4.630s	319.961us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	4.630s	319.961us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.160s	36.055us	5	5	100.00
		keymgr_csr_rw	1.470s	26.510us	20	20	100.00
		keymgr_csr_aliasing	7.870s	1.386ms	5	5	100.00
		keymgr_same_csr_outstanding	3.760s	90.672us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.160s	36.055us	5	5	100.00
		keymgr_csr_rw	1.470s	26.510us	20	20	100.00
		keymgr_csr_aliasing	7.870s	1.386ms	5	5	100.00
		keymgr_same_csr_outstanding	3.760s	90.672us	20	20	100.00
V2		TOTAL			736	740	99.46
V2S	sec_cm_additional_check	keymgr_sec_cm	12.970s	2.525ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	12.970s	2.525ms	5	5	100.00
		keymgr_tl_intg_err	10.750s	1.198ms	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	5.340s	606.318us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	5.340s	606.318us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	5.340s	606.318us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	5.340s	606.318us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	14.410s	440.848us	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	12.970s	2.525ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	12.970s	2.525ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	10.750s	1.198ms	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	5.340s	606.318us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.351m	3.605ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	1.264m	2.432ms	50	50	100.00
		keymgr_csr_rw	1.470s	26.510us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	1.264m	2.432ms	50	50	100.00
		keymgr_csr_rw	1.470s	26.510us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	1.264m	2.432ms	50	50	100.00
		keymgr_csr_rw	1.470s	26.510us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	19.180s	1.508ms	49	50	98.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	56.280s	8.242ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	56.280s	8.242ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	1.264m	2.432ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	28.890s	2.861ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	12.970s	2.525ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	12.970s	2.525ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	12.970s	2.525ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	18.370s	1.245ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	19.180s	1.508ms	49	50	98.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	12.970s	2.525ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	12.970s	2.525ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	12.970s	2.525ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	18.370s	1.245ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	18.370s	1.245ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	12.970s	2.525ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	18.370s	1.245ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	12.970s	2.525ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	18.370s	1.245ms	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	30.670s	1.940ms	30	50	60.00
V3		TOTAL			30	50	60.00
		TOTAL			1086	1110	97.84

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	16	16	13	81.25
V2S	6	6	6	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.72	99.04	98.07	98.33	100.00	99.02	98.41	91.17

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:
- Test keymgr_stress_all_with_rand_reset has 20 failures.
  - 2.keymgr_stress_all_with_rand_reset.80700398121854524399016080297295931202684146930148230188363302134131926946392
    Line 338, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/2.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 448405142 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 448405142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.keymgr_stress_all_with_rand_reset.94741144835257007735529222606243483846460296521649497048801031665876979297361
    Line 478, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/5.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1598316545 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1598316545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 18 more failures.
UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 2 failures:
- Test keymgr_sideload_aes has 2 failures.
  - 10.keymgr_sideload_aes.108220932123667936272556771096201403050525022575394517593247049802768259324551
    Line 268, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/10.keymgr_sideload_aes/latest/run.log
```
  UVM_ERROR @  24190351 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @  24190351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 41.keymgr_sideload_aes.100423797231253219995696876209543999612004568836192515579875485211304033874284
    Line 273, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/41.keymgr_sideload_aes/latest/run.log
```
  UVM_ERROR @  25223256 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @  25223256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data !=gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share0_output_*` has 1 failures:
- Test keymgr_lc_disable has 1 failures.
  - 32.keymgr_lc_disable.49294811722773596333060416549747475537136503752389371122578448627518475159690
    Line 369, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/32.keymgr_lc_disable/latest/run.log
```
  UVM_ERROR @  19441763 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (3180643976 [0xbd94c688] vs 3180643976 [0xbd94c688]) reg name: keymgr_reg_block.sw_share0_output_5
  UVM_INFO @  19441763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) AES key at state StOwnerIntKey for Sealing Aes has 1 failures:

Test keymgr_stress_all has 1 failures.

40.keymgr_stress_all.42431957869303968600935510919022555025034880464727516827441414621042508886051
Line 1762, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/40.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 740225936 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (2996030658114105323874622250324640591404198422214424460952901115220751636594546918163971315627573630299178283184620924603772802447213563473494312068645605 [0x39344af5525a274c0452d2558ea0dcba44d438ae344b1a788eb797517347c66cb4def8c0fced626e15104fd509e53ce1dde827b998db30673cd667bebd1102e5] vs 2996030658114105323874622250324640591404198422214424460952901115220751636594546918163971315627573630299178283184620924603772802447213563473494312068645605 [0x39344af5525a274c0452d2558ea0dcba44d438ae344b1a788eb797517347c66cb4def8c0fced626e15104fd509e53ce1dde827b998db30673cd667bebd1102e5]) AES key at state StOwnerIntKey for Sealing Aes
  UVM_INFO @ 740225936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---