2e5d86c9b5
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | keymgr_smoke | 29.700s | 2.760ms | 50 | 50 | 100.00 |
V1 | random | keymgr_random | 1.556m | 38.060ms | 50 | 50 | 100.00 |
V1 | csr_hw_reset | keymgr_csr_hw_reset | 1.080s | 58.589us | 5 | 5 | 100.00 |
V1 | csr_rw | keymgr_csr_rw | 1.710s | 32.292us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | keymgr_csr_bit_bash | 25.590s | 3.553ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | keymgr_csr_aliasing | 9.640s | 459.680us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | keymgr_csr_mem_rw_with_rand_reset | 2.730s | 41.012us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | keymgr_csr_rw | 1.710s | 32.292us | 20 | 20 | 100.00 |
keymgr_csr_aliasing | 9.640s | 459.680us | 5 | 5 | 100.00 | ||
V1 | TOTAL | 155 | 155 | 100.00 | |||
V2 | cfgen_during_op | keymgr_cfg_regwen | 1.183m | 1.276ms | 49 | 50 | 98.00 |
V2 | sideload | keymgr_sideload | 51.820s | 4.749ms | 50 | 50 | 100.00 |
keymgr_sideload_kmac | 43.520s | 6.389ms | 50 | 50 | 100.00 | ||
keymgr_sideload_aes | 1.087m | 7.120ms | 50 | 50 | 100.00 | ||
keymgr_sideload_otbn | 57.480s | 1.851ms | 50 | 50 | 100.00 | ||
V2 | direct_to_disabled_state | keymgr_direct_to_disabled | 15.850s | 1.587ms | 50 | 50 | 100.00 |
V2 | lc_disable | keymgr_lc_disable | 19.110s | 677.285us | 47 | 50 | 94.00 |
V2 | kmac_error_response | keymgr_kmac_rsp_err | 8.600s | 903.985us | 50 | 50 | 100.00 |
V2 | invalid_sw_input | keymgr_sw_invalid_input | 1.280m | 2.175ms | 50 | 50 | 100.00 |
V2 | invalid_hw_input | keymgr_hwsw_invalid_input | 1.124m | 3.788ms | 50 | 50 | 100.00 |
V2 | sync_async_fault_cross | keymgr_sync_async_fault_cross | 20.010s | 879.078us | 49 | 50 | 98.00 |
V2 | stress_all | keymgr_stress_all | 6.726m | 34.235ms | 46 | 50 | 92.00 |
V2 | intr_test | keymgr_intr_test | 0.950s | 137.940us | 50 | 50 | 100.00 |
V2 | alert_test | keymgr_alert_test | 1.180s | 30.215us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | keymgr_tl_errors | 4.870s | 236.013us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | keymgr_tl_errors | 4.870s | 236.013us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | keymgr_csr_hw_reset | 1.080s | 58.589us | 5 | 5 | 100.00 |
keymgr_csr_rw | 1.710s | 32.292us | 20 | 20 | 100.00 | ||
keymgr_csr_aliasing | 9.640s | 459.680us | 5 | 5 | 100.00 | ||
keymgr_same_csr_outstanding | 3.690s | 93.731us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | keymgr_csr_hw_reset | 1.080s | 58.589us | 5 | 5 | 100.00 |
keymgr_csr_rw | 1.710s | 32.292us | 20 | 20 | 100.00 | ||
keymgr_csr_aliasing | 9.640s | 459.680us | 5 | 5 | 100.00 | ||
keymgr_same_csr_outstanding | 3.690s | 93.731us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 731 | 740 | 98.78 | |||
V2S | sec_cm_additional_check | keymgr_sec_cm | 32.100s | 1.488ms | 5 | 5 | 100.00 |
V2S | tl_intg_err | keymgr_sec_cm | 32.100s | 1.488ms | 5 | 5 | 100.00 |
keymgr_tl_intg_err | 9.170s | 4.364ms | 20 | 20 | 100.00 | ||
V2S | shadow_reg_update_error | keymgr_shadow_reg_errors | 4.890s | 179.735us | 20 | 20 | 100.00 |
V2S | shadow_reg_read_clear_staged_value | keymgr_shadow_reg_errors | 4.890s | 179.735us | 20 | 20 | 100.00 |
V2S | shadow_reg_storage_error | keymgr_shadow_reg_errors | 4.890s | 179.735us | 20 | 20 | 100.00 |
V2S | shadowed_reset_glitch | keymgr_shadow_reg_errors | 4.890s | 179.735us | 20 | 20 | 100.00 |
V2S | shadow_reg_update_error_with_csr_rw | keymgr_shadow_reg_errors_with_csr_rw | 15.220s | 413.102us | 20 | 20 | 100.00 |
V2S | prim_count_check | keymgr_sec_cm | 32.100s | 1.488ms | 5 | 5 | 100.00 |
V2S | prim_fsm_check | keymgr_sec_cm | 32.100s | 1.488ms | 5 | 5 | 100.00 |
V2S | sec_cm_bus_integrity | keymgr_tl_intg_err | 9.170s | 4.364ms | 20 | 20 | 100.00 |
V2S | sec_cm_config_shadow | keymgr_shadow_reg_errors | 4.890s | 179.735us | 20 | 20 | 100.00 |
V2S | sec_cm_op_config_regwen | keymgr_cfg_regwen | 1.183m | 1.276ms | 49 | 50 | 98.00 |
V2S | sec_cm_reseed_config_regwen | keymgr_random | 1.556m | 38.060ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.710s | 32.292us | 20 | 20 | 100.00 | ||
V2S | sec_cm_sw_binding_config_regwen | keymgr_random | 1.556m | 38.060ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.710s | 32.292us | 20 | 20 | 100.00 | ||
V2S | sec_cm_max_key_ver_config_regwen | keymgr_random | 1.556m | 38.060ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.710s | 32.292us | 20 | 20 | 100.00 | ||
V2S | sec_cm_lc_ctrl_intersig_mubi | keymgr_lc_disable | 19.110s | 677.285us | 47 | 50 | 94.00 |
V2S | sec_cm_constants_consistency | keymgr_hwsw_invalid_input | 1.124m | 3.788ms | 50 | 50 | 100.00 |
V2S | sec_cm_intersig_consistency | keymgr_hwsw_invalid_input | 1.124m | 3.788ms | 50 | 50 | 100.00 |
V2S | sec_cm_hw_key_sw_noaccess | keymgr_random | 1.556m | 38.060ms | 50 | 50 | 100.00 |
V2S | sec_cm_output_keys_ctrl_redun | keymgr_sideload_protect | 17.250s | 1.566ms | 50 | 50 | 100.00 |
V2S | sec_cm_ctrl_fsm_sparse | keymgr_sec_cm | 32.100s | 1.488ms | 5 | 5 | 100.00 |
V2S | sec_cm_data_fsm_sparse | keymgr_sec_cm | 32.100s | 1.488ms | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_fsm_local_esc | keymgr_sec_cm | 32.100s | 1.488ms | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_fsm_consistency | keymgr_custom_cm | 33.990s | 888.442us | 50 | 50 | 100.00 |
V2S | sec_cm_ctrl_fsm_global_esc | keymgr_lc_disable | 19.110s | 677.285us | 47 | 50 | 94.00 |
V2S | sec_cm_ctrl_ctr_redun | keymgr_sec_cm | 32.100s | 1.488ms | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_fsm_sparse | keymgr_sec_cm | 32.100s | 1.488ms | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_ctr_redun | keymgr_sec_cm | 32.100s | 1.488ms | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_cmd_ctrl_consistency | keymgr_custom_cm | 33.990s | 888.442us | 50 | 50 | 100.00 |
V2S | sec_cm_kmac_if_done_ctrl_consistency | keymgr_custom_cm | 33.990s | 888.442us | 50 | 50 | 100.00 |
V2S | sec_cm_reseed_ctr_redun | keymgr_sec_cm | 32.100s | 1.488ms | 5 | 5 | 100.00 |
V2S | sec_cm_side_load_sel_ctrl_consistency | keymgr_custom_cm | 33.990s | 888.442us | 50 | 50 | 100.00 |
V2S | sec_cm_sideload_ctrl_fsm_sparse | keymgr_sec_cm | 32.100s | 1.488ms | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_key_integrity | keymgr_custom_cm | 33.990s | 888.442us | 50 | 50 | 100.00 |
V2S | TOTAL | 165 | 165 | 100.00 | |||
V3 | stress_all_with_rand_reset | keymgr_stress_all_with_rand_reset | 28.100s | 2.416ms | 31 | 50 | 62.00 |
V3 | TOTAL | 31 | 50 | 62.00 | |||
TOTAL | 1082 | 1110 | 97.48 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 7 | 7 | 7 | 100.00 |
V2 | 16 | 16 | 12 | 75.00 |
V2S | 6 | 6 | 6 | 100.00 |
V3 | 1 | 1 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
97.40 | 99.00 | 98.23 | 98.42 | 97.67 | 98.93 | 98.41 | 91.14 |
UVM_ERROR (cip_base_vseq.sv:825) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
has 17 failures:
1.keymgr_stress_all_with_rand_reset.46350102842022273982479817419806731198697573854628421143418574581487518178601
Line 605, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 510863094 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 510863094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.keymgr_stress_all_with_rand_reset.112371212730404315146562038557916619340724517080858414424139244429094629490827
Line 603, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/3.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 897836149 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 897836149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 15 more failures.
UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:*
has 5 failures:
Test keymgr_lc_disable has 1 failures.
3.keymgr_lc_disable.76997406905160014609520235475497527886458808865719733603766025364784002098530
Line 388, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/3.keymgr_lc_disable/latest/run.log
UVM_ERROR @ 7282128 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
UVM_INFO @ 7282128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test keymgr_stress_all_with_rand_reset has 1 failures.
5.keymgr_stress_all_with_rand_reset.83873863445074075886958214044874894522736694790180751733697799533823416496727
Line 871, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/5.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 139894473 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
UVM_INFO @ 139894473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test keymgr_stress_all has 3 failures.
24.keymgr_stress_all.112273811595553915098644789210257439293746789972349945103035150714080744957904
Line 630, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/24.keymgr_stress_all/latest/run.log
UVM_ERROR @ 25855255 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
UVM_INFO @ 25855255 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
27.keymgr_stress_all.35086539430834116870788497093588919942163874983930085294702688759346302246115
Line 1746, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/27.keymgr_stress_all/latest/run.log
UVM_ERROR @ 1189599647 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
UVM_INFO @ 1189599647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data !=
gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share1_output_*` has 2 failures:
36.keymgr_lc_disable.32084868606365603360075914800883326709200791705389313941594157345963832516153
Line 519, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/36.keymgr_lc_disable/latest/run.log
UVM_ERROR @ 337229806 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share1_output_2
UVM_INFO @ 337229806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
48.keymgr_lc_disable.44542331893901711159665929442368122546605960959097281564694240916419957531885
Line 511, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/48.keymgr_lc_disable/latest/run.log
UVM_ERROR @ 92275278 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (95596564 [0x5b2b014] vs 95596564 [0x5b2b014]) reg name: keymgr_reg_block.sw_share1_output_3
UVM_INFO @ 92275278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:794) [scoreboard] Check failed item.d_data ==
gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.start` has 1 failures:
7.keymgr_cfg_regwen.25391299648363956110048818772322655393813125797559097544615817428351438229840
Line 261, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/7.keymgr_cfg_regwen/latest/run.log
UVM_ERROR @ 14360789 ps: (keymgr_scoreboard.sv:794) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 1 [0x1]) reg name: keymgr_reg_block.start
UVM_INFO @ 14360789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_sync_async_fault_cross_vseq.sv:38) [keymgr_sync_async_fault_cross_vseq] Check failed act_fault_status[keymgr_pkg::FaultKmacOp] || act_fault_status[keymgr_pkg::FaultKmacOut] == * (* [*] vs * [*])
has 1 failures:
10.keymgr_sync_async_fault_cross.100415522916867481837630582944668939870328596056073966832907776007232154690502
Line 342, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/10.keymgr_sync_async_fault_cross/latest/run.log
UVM_ERROR @ 206932401 ps: (keymgr_sync_async_fault_cross_vseq.sv:38) [uvm_test_top.env.virtual_sequencer.keymgr_sync_async_fault_cross_vseq] Check failed act_fault_status[keymgr_pkg::FaultKmacOp] || act_fault_status[keymgr_pkg::FaultKmacOut] == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 206932401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) AES key at state StCreatorRootKey for Sealing Aes
has 1 failures:
37.keymgr_stress_all.92832850472978836068979354552954449082887253830045191525666059614590950508430
Line 912, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/37.keymgr_stress_all/latest/run.log
UVM_ERROR @ 673281604 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (2223305188913972574212485953901890578584519347203189987442094237965066924947816862621614733226154461069273380383831500903801298649746954863089056578533473 [0x2a734a157717b733089290ce7236c3de5c5e234f9a3d06aac8fe6738dcf66d2530613c5c6bed63bea8e7beac14a596f1fe955ef19ecbabfb5017f35094cbf861] vs 2223305188913972574212485953901890578584519347203189987442094237965066924947816862621614733226154461069273380383831500903801298649746954863089056578533473 [0x2a734a157717b733089290ce7236c3de5c5e234f9a3d06aac8fe6738dcf66d2530613c5c6bed63bea8e7beac14a596f1fe955ef19ecbabfb5017f35094cbf861]) AES key at state StCreatorRootKey for Sealing Aes
UVM_INFO @ 673281604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:692) [scoreboard] Check failed item.d_data == addr_phase_op_status (* [*] vs * [*])
has 1 failures:
40.keymgr_stress_all_with_rand_reset.112822828195519413383871868108980432302601774296357618609369968526190318949674
Line 653, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/40.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 504251581 ps: (keymgr_scoreboard.sv:692) [uvm_test_top.env.scoreboard] Check failed item.d_data == addr_phase_op_status (1 [0x1] vs 2 [0x2])
UVM_INFO @ 504251581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---