KEYMGR Simulation Results

Tuesday July 09 2024 23:02:48 UTC

GitHub Revision: 6a84251492

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 61727890964832844865465694323650730626175387240181955975848876152363892893427

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	23.040s	1.184ms	50	50	100.00
V1	random	keymgr_random	58.700s	8.620ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.450s	253.812us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.720s	111.831us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	16.470s	4.463ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	10.300s	725.515us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.200s	91.870us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.720s	111.831us	20	20	100.00
		keymgr_csr_aliasing	10.300s	725.515us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	1.468m	5.956ms	50	50	100.00
V2	sideload	keymgr_sideload	44.750s	1.437ms	50	50	100.00
		keymgr_sideload_kmac	55.400s	1.897ms	50	50	100.00
		keymgr_sideload_aes	1.009m	1.778ms	50	50	100.00
		keymgr_sideload_otbn	53.770s	1.724ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	32.970s	4.833ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	17.260s	1.169ms	50	50	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	23.400s	2.338ms	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	1.152m	25.582ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	11.800s	3.468ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	30.310s	8.811ms	50	50	100.00
V2	stress_all	keymgr_stress_all	7.127m	24.725ms	48	50	96.00
V2	intr_test	keymgr_intr_test	1.020s	28.195us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.120s	79.373us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	4.020s	195.562us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	4.020s	195.562us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.450s	253.812us	5	5	100.00
		keymgr_csr_rw	1.720s	111.831us	20	20	100.00
		keymgr_csr_aliasing	10.300s	725.515us	5	5	100.00
		keymgr_same_csr_outstanding	4.330s	189.254us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.450s	253.812us	5	5	100.00
		keymgr_csr_rw	1.720s	111.831us	20	20	100.00
		keymgr_csr_aliasing	10.300s	725.515us	5	5	100.00
		keymgr_same_csr_outstanding	4.330s	189.254us	20	20	100.00
V2		TOTAL			738	740	99.73
V2S	sec_cm_additional_check	keymgr_sec_cm	16.650s	1.040ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	16.650s	1.040ms	5	5	100.00
		keymgr_tl_intg_err	9.680s	249.784us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	5.720s	240.963us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	5.720s	240.963us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	5.720s	240.963us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	5.720s	240.963us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	15.780s	1.771ms	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	16.650s	1.040ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	16.650s	1.040ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	9.680s	249.784us	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	5.720s	240.963us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.468m	5.956ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	58.700s	8.620ms	50	50	100.00
		keymgr_csr_rw	1.720s	111.831us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	58.700s	8.620ms	50	50	100.00
		keymgr_csr_rw	1.720s	111.831us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	58.700s	8.620ms	50	50	100.00
		keymgr_csr_rw	1.720s	111.831us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	17.260s	1.169ms	50	50	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	11.800s	3.468ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	11.800s	3.468ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	58.700s	8.620ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	33.250s	5.528ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	16.650s	1.040ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	16.650s	1.040ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	16.650s	1.040ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	51.460s	1.758ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	17.260s	1.169ms	50	50	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	16.650s	1.040ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	16.650s	1.040ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	16.650s	1.040ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	51.460s	1.758ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	51.460s	1.758ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	16.650s	1.040ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	51.460s	1.758ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	16.650s	1.040ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	51.460s	1.758ms	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	26.230s	2.279ms	27	50	54.00
V3		TOTAL			27	50	54.00
		TOTAL			1085	1110	97.75

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	16	16	15	93.75
V2S	6	6	6	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.72	99.04	97.99	98.42	100.00	99.02	98.41	91.19

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:825) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:

  • Test keymgr_stress_all_with_rand_reset has 23 failures.

    • 0.keymgr_stress_all_with_rand_reset.49408617693066143777730818556101463564037129467033294821647755890977321500453
      Line 917, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 346716504 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 346716504 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.keymgr_stress_all_with_rand_reset.46844988083907873021521074879303160941597368077683379311002772876090597275450
      Line 832, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 877567890 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 877567890 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 21 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 1 failures:

  • Test keymgr_stress_all has 1 failures.

    • 10.keymgr_stress_all.113715774036451884203508244883150852138356670040387283848217808133195570459536
      Line 673, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/10.keymgr_stress_all/latest/run.log

        UVM_ERROR @ 225605484 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:2000
        UVM_INFO @ 225605484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data !=gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share1_output_*` has 1 failures:

  • Test keymgr_stress_all has 1 failures.

    • 39.keymgr_stress_all.113357287983620348961851068318492774333817219157663780123530760096884942627867
      Line 4896, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/39.keymgr_stress_all/latest/run.log

        UVM_ERROR @ 4299347284 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share1_output_1
        UVM_INFO @ 4299347284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• lint
• 2024.07.08_10.09.00
• 2024.07.07_10.32.07
• 2024.07.06_10.39.02
• 2024.07.05_11.03.54
• 2024.07.04_11.12.43
• 2024.07.03_01.46.26