KEYMGR Simulation Results

Wednesday July 10 2024 23:02:26 UTC

GitHub Revision: `39211701b5`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 52262812535389540465251148247405743574935129745685597413714598750252192397067

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	45.470s	6.053ms	50	50	100.00
V1	random	keymgr_random	1.408m	21.273ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.240s	190.980us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.610s	27.598us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	24.160s	1.952ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	8.360s	2.566ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.450s	122.867us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.610s	27.598us	20	20	100.00
		keymgr_csr_aliasing	8.360s	2.566ms	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	1.815m	2.251ms	50	50	100.00
V2	sideload	keymgr_sideload	45.650s	12.777ms	50	50	100.00
		keymgr_sideload_kmac	40.050s	3.917ms	50	50	100.00
		keymgr_sideload_aes	41.360s	2.451ms	50	50	100.00
		keymgr_sideload_otbn	47.720s	1.583ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	31.910s	4.036ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	5.890s	3.629ms	49	50	98.00
V2	kmac_error_response	keymgr_kmac_rsp_err	8.340s	289.309us	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	1.071m	5.601ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	48.030s	3.846ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	24.210s	2.651ms	49	50	98.00
V2	stress_all	keymgr_stress_all	7.434m	19.327ms	48	50	96.00
V2	intr_test	keymgr_intr_test	0.920s	11.954us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.090s	105.844us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	5.910s	691.574us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	5.910s	691.574us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.240s	190.980us	5	5	100.00
		keymgr_csr_rw	1.610s	27.598us	20	20	100.00
		keymgr_csr_aliasing	8.360s	2.566ms	5	5	100.00
		keymgr_same_csr_outstanding	4.470s	109.741us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.240s	190.980us	5	5	100.00
		keymgr_csr_rw	1.610s	27.598us	20	20	100.00
		keymgr_csr_aliasing	8.360s	2.566ms	5	5	100.00
		keymgr_same_csr_outstanding	4.470s	109.741us	20	20	100.00
V2		TOTAL			736	740	99.46
V2S	sec_cm_additional_check	keymgr_sec_cm	13.390s	9.059ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	13.390s	9.059ms	5	5	100.00
		keymgr_tl_intg_err	10.350s	356.557us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	5.450s	1.130ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	5.450s	1.130ms	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	5.450s	1.130ms	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	5.450s	1.130ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	15.850s	877.054us	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	13.390s	9.059ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	13.390s	9.059ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	10.350s	356.557us	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	5.450s	1.130ms	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.815m	2.251ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	1.408m	21.273ms	50	50	100.00
		keymgr_csr_rw	1.610s	27.598us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	1.408m	21.273ms	50	50	100.00
		keymgr_csr_rw	1.610s	27.598us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	1.408m	21.273ms	50	50	100.00
		keymgr_csr_rw	1.610s	27.598us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	5.890s	3.629ms	49	50	98.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	48.030s	3.846ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	48.030s	3.846ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	1.408m	21.273ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	24.450s	1.365ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	13.390s	9.059ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	13.390s	9.059ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	13.390s	9.059ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	31.660s	3.939ms	49	50	98.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	5.890s	3.629ms	49	50	98.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	13.390s	9.059ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	13.390s	9.059ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	13.390s	9.059ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	31.660s	3.939ms	49	50	98.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	31.660s	3.939ms	49	50	98.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	13.390s	9.059ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	31.660s	3.939ms	49	50	98.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	13.390s	9.059ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	31.660s	3.939ms	49	50	98.00
V2S		TOTAL			164	165	99.39
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	22.820s	2.369ms	29	50	58.00
V3		TOTAL			29	50	58.00
		TOTAL			1084	1110	97.66

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	16	16	13	81.25
V2S	6	6	5	83.33
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.71	99.04	97.91	98.33	100.00	99.02	98.41	91.24

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 18 failures:
- Test keymgr_stress_all_with_rand_reset has 18 failures.
  - 0.keymgr_stress_all_with_rand_reset.45650119617721607662833677214039668480638834064815697157284572865967605479180
    Line 592, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1250365262 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1250365262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.keymgr_stress_all_with_rand_reset.37716365264384221082145838665830510074647767089326300535579783440635995933024
    Line 358, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/2.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 807325086 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 807325086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 16 more failures.

UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 4 failures:

Test keymgr_custom_cm has 1 failures.

9.keymgr_custom_cm.21685721745561882783199902523007601923471372688505923904858559768027963155198
Line 263, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/9.keymgr_custom_cm/latest/run.log

  UVM_ERROR @   3350048 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @   3350048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_stress_all has 2 failures.

17.keymgr_stress_all.66398068812494008190422029626098910084416520717897082053695187989098228323779
Line 1919, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/17.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 276450582 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @ 276450582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

19.keymgr_stress_all.7206145124315426955066511693711351796130824019660456314256219164159595015969
Line 3453, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/19.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 768554182 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @ 768554182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_sync_async_fault_cross has 1 failures.
- 44.keymgr_sync_async_fault_cross.90024105826013959438530215003949352097760600335775565518248866303525931625432
  Line 273, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/44.keymgr_sync_async_fault_cross/latest/run.log
```
  UVM_ERROR @   2962078 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @   2962078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_vseq.sv:749) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 3 failures:
- Test keymgr_stress_all_with_rand_reset has 3 failures.
  - 6.keymgr_stress_all_with_rand_reset.108844803195697240723581538260764929417300393410084231409963182698655784457361
    Line 593, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/6.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1017814534 ps: (cip_base_vseq.sv:749) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1017814534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 23.keymgr_stress_all_with_rand_reset.29630858788540952763742614896181064231453851486607904911885557417741273856954
    Line 1618, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/23.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1195881405 ps: (cip_base_vseq.sv:749) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1195881405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data !=gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share0_output_*` has 1 failures:
- Test keymgr_lc_disable has 1 failures.
  - 24.keymgr_lc_disable.58698178427585202084058428158712156646846275957993840440730220188882389591218
    Line 472, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/24.keymgr_lc_disable/latest/run.log
```
  UVM_ERROR @ 145870743 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share0_output_7
  UVM_INFO @ 145870743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```