KEYMGR Simulation Results

Thursday July 11 2024 23:02:31 UTC

GitHub Revision: edf2fd5092

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 110991919330983905489672005724934609038320729526710604109871030362225161447318

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	41.470s	14.993ms	50	50	100.00
V1	random	keymgr_random	1.450m	2.832ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.460s	389.832us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.270s	44.405us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	24.640s	6.520ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	9.090s	1.172ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.380s	35.307us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.270s	44.405us	20	20	100.00
		keymgr_csr_aliasing	9.090s	1.172ms	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	1.475m	2.390ms	50	50	100.00
V2	sideload	keymgr_sideload	43.030s	2.111ms	50	50	100.00
		keymgr_sideload_kmac	52.650s	1.834ms	50	50	100.00
		keymgr_sideload_aes	35.580s	2.954ms	50	50	100.00
		keymgr_sideload_otbn	48.260s	17.226ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	30.220s	1.116ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	10.110s	207.002us	49	50	98.00
V2	kmac_error_response	keymgr_kmac_rsp_err	14.820s	2.925ms	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	57.840s	3.494ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	47.370s	2.558ms	49	50	98.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	10.540s	396.070us	50	50	100.00
V2	stress_all	keymgr_stress_all	7.405m	57.876ms	48	50	96.00
V2	intr_test	keymgr_intr_test	1.070s	30.053us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.050s	89.031us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	5.860s	317.752us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	5.860s	317.752us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.460s	389.832us	5	5	100.00
		keymgr_csr_rw	1.270s	44.405us	20	20	100.00
		keymgr_csr_aliasing	9.090s	1.172ms	5	5	100.00
		keymgr_same_csr_outstanding	4.600s	947.178us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.460s	389.832us	5	5	100.00
		keymgr_csr_rw	1.270s	44.405us	20	20	100.00
		keymgr_csr_aliasing	9.090s	1.172ms	5	5	100.00
		keymgr_same_csr_outstanding	4.600s	947.178us	20	20	100.00
V2		TOTAL			736	740	99.46
V2S	sec_cm_additional_check	keymgr_sec_cm	12.350s	500.986us	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	12.350s	500.986us	5	5	100.00
		keymgr_tl_intg_err	10.900s	1.097ms	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	4.230s	124.200us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	4.230s	124.200us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	4.230s	124.200us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	4.230s	124.200us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	17.520s	528.110us	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	12.350s	500.986us	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	12.350s	500.986us	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	10.900s	1.097ms	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	4.230s	124.200us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.475m	2.390ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	1.450m	2.832ms	50	50	100.00
		keymgr_csr_rw	1.270s	44.405us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	1.450m	2.832ms	50	50	100.00
		keymgr_csr_rw	1.270s	44.405us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	1.450m	2.832ms	50	50	100.00
		keymgr_csr_rw	1.270s	44.405us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	10.110s	207.002us	49	50	98.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	47.370s	2.558ms	49	50	98.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	47.370s	2.558ms	49	50	98.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	1.450m	2.832ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	19.680s	6.715ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	12.350s	500.986us	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	12.350s	500.986us	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	12.350s	500.986us	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	37.190s	1.454ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	10.110s	207.002us	49	50	98.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	12.350s	500.986us	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	12.350s	500.986us	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	12.350s	500.986us	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	37.190s	1.454ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	37.190s	1.454ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	12.350s	500.986us	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	37.190s	1.454ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	12.350s	500.986us	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	37.190s	1.454ms	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	28.040s	586.917us	33	50	66.00
V3		TOTAL			33	50	66.00
		TOTAL			1089	1110	98.11

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	16	16	13	81.25
V2S	6	6	6	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.73	99.04	98.15	98.38	100.00	99.02	98.41	91.14

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:825) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 16 failures:

  • Test keymgr_stress_all_with_rand_reset has 16 failures.

    • 3.keymgr_stress_all_with_rand_reset.63127020907275160970568243693356182646546082991671383654337345309041597175302
      Line 1317, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/3.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 484060925 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 484060925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 4.keymgr_stress_all_with_rand_reset.110118667738344928191121293974420479654451126054951951861013010601381820256594
      Line 514, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/4.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 849727576 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 849727576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 14 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 2 failures:

  • Test keymgr_stress_all has 1 failures.

    • 6.keymgr_stress_all.46879489744084141481873119121575917684673284353655324033290867083827803837346
      Line 449, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/6.keymgr_stress_all/latest/run.log

        UVM_ERROR @  40239850 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
        UVM_INFO @  40239850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_hwsw_invalid_input has 1 failures.

    • 43.keymgr_hwsw_invalid_input.11025298478015100058550201752562798026499344143163249246117568971984887001685
      Line 346, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/43.keymgr_hwsw_invalid_input/latest/run.log

        UVM_ERROR @  71772870 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
        UVM_INFO @  71772870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data !=gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share0_output_*` has 1 failures:

  • Test keymgr_stress_all has 1 failures.

    • 2.keymgr_stress_all.11245775827402277649866783502775677189804115960678996244399117043645524667548
      Line 3717, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/2.keymgr_stress_all/latest/run.log

        UVM_ERROR @ 5212174769 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share0_output_1
        UVM_INFO @ 5212174769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:749) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test keymgr_stress_all_with_rand_reset has 1 failures.

    • 10.keymgr_stress_all_with_rand_reset.59368330129605763996486894787041332297425101244952082406020568681308697268890
      Line 490, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/10.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 507054098 ps: (cip_base_vseq.sv:749) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 507054098 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (keymgr_scoreboard.sv:651) [scoreboard] Check failed act_state == addr_phase_working_state (* [*] vs * [*]) has 1 failures:

  • Test keymgr_lc_disable has 1 failures.

    • 13.keymgr_lc_disable.81814399085940446420365984905689428580074662714818526847843782688055193548606
      Line 506, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/13.keymgr_lc_disable/latest/run.log

        UVM_ERROR @ 131233253 ps: (keymgr_scoreboard.sv:651) [uvm_test_top.env.scoreboard] Check failed act_state == addr_phase_working_state (5 [0x5] vs 6 [0x6])
        UVM_INFO @ 131233253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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