KEYMGR Simulation Results

Friday July 12 2024 23:02:19 UTC

GitHub Revision: `5967df933a`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 46476530947956470787268850137993439884379231200278174763551439909664842175844

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	40.370s	4.784ms	50	50	100.00
V1	random	keymgr_random	43.710s	3.423ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.370s	23.607us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.600s	73.712us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	16.690s	1.281ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	11.830s	1.826ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.250s	631.112us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.600s	73.712us	20	20	100.00
		keymgr_csr_aliasing	11.830s	1.826ms	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	1.473m	16.236ms	50	50	100.00
V2	sideload	keymgr_sideload	33.400s	3.115ms	50	50	100.00
		keymgr_sideload_kmac	49.460s	4.469ms	50	50	100.00
		keymgr_sideload_aes	43.800s	6.546ms	50	50	100.00
		keymgr_sideload_otbn	27.750s	856.101us	49	50	98.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	38.900s	5.158ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	26.810s	1.939ms	50	50	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	13.820s	4.018ms	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	1.188m	6.233ms	49	50	98.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	21.630s	1.063ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	19.470s	2.163ms	50	50	100.00
V2	stress_all	keymgr_stress_all	7.596m	62.101ms	50	50	100.00
V2	intr_test	keymgr_intr_test	0.910s	42.063us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.090s	39.321us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	4.940s	349.806us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	4.940s	349.806us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.370s	23.607us	5	5	100.00
		keymgr_csr_rw	1.600s	73.712us	20	20	100.00
		keymgr_csr_aliasing	11.830s	1.826ms	5	5	100.00
		keymgr_same_csr_outstanding	3.700s	124.745us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.370s	23.607us	5	5	100.00
		keymgr_csr_rw	1.600s	73.712us	20	20	100.00
		keymgr_csr_aliasing	11.830s	1.826ms	5	5	100.00
		keymgr_same_csr_outstanding	3.700s	124.745us	20	20	100.00
V2		TOTAL			738	740	99.73
V2S	sec_cm_additional_check	keymgr_sec_cm	18.260s	3.814ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	18.260s	3.814ms	5	5	100.00
		keymgr_tl_intg_err	10.660s	1.343ms	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	4.620s	188.871us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	4.620s	188.871us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	4.620s	188.871us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	4.620s	188.871us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	15.360s	993.280us	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	18.260s	3.814ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	18.260s	3.814ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	10.660s	1.343ms	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	4.620s	188.871us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.473m	16.236ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	43.710s	3.423ms	50	50	100.00
		keymgr_csr_rw	1.600s	73.712us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	43.710s	3.423ms	50	50	100.00
		keymgr_csr_rw	1.600s	73.712us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	43.710s	3.423ms	50	50	100.00
		keymgr_csr_rw	1.600s	73.712us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	26.810s	1.939ms	50	50	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	21.630s	1.063ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	21.630s	1.063ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	43.710s	3.423ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	21.490s	732.434us	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	18.260s	3.814ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	18.260s	3.814ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	18.260s	3.814ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	34.890s	2.372ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	26.810s	1.939ms	50	50	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	18.260s	3.814ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	18.260s	3.814ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	18.260s	3.814ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	34.890s	2.372ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	34.890s	2.372ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	18.260s	3.814ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	34.890s	2.372ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	18.260s	3.814ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	34.890s	2.372ms	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	40.790s	3.540ms	30	50	60.00
V3		TOTAL			30	50	60.00
		TOTAL			1088	1110	98.02

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	16	16	14	87.50
V2S	6	6	6	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.72	99.04	97.99	98.49	100.00	99.02	98.41	91.09

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 19 failures:
- Test keymgr_stress_all_with_rand_reset has 19 failures.
  - 3.keymgr_stress_all_with_rand_reset.46694449601202418111565285318659146359285515833763207892119246829607078038884
    Line 460, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/3.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 144920270 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10002 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 144920270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.keymgr_stress_all_with_rand_reset.10731438652316228991982096395089812563315294209247981122034161414614688505398
    Line 804, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/4.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 527725928 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 527725928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 17 more failures.
UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 2 failures:
- Test keymgr_sideload_otbn has 1 failures.
  - 27.keymgr_sideload_otbn.90211839740053503307308946996115085367840941499422334599508996654290243839850
    Line 269, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/27.keymgr_sideload_otbn/latest/run.log
```
  UVM_ERROR @   4890540 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @   4890540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test keymgr_sw_invalid_input has 1 failures.
  - 42.keymgr_sw_invalid_input.78027388786450548670217982641931960594209026956987739026791162694000231004592
    Line 374, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/42.keymgr_sw_invalid_input/latest/run.log
```
  UVM_ERROR @  19092469 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @  19092469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (keymgr_scoreboard.sv:1064) [scoreboard] Check failed act == exp (* [*] vs * [*]) cdi_type: Attestation has 1 failures:

Test keymgr_stress_all_with_rand_reset has 1 failures.

23.keymgr_stress_all_with_rand_reset.85160452679019047571011331870358820141875893976525072587381250779096288430459
Line 426, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/23.keymgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 211336301 ps: (keymgr_scoreboard.sv:1064) [uvm_test_top.env.scoreboard] Check failed act == exp (59235776249019536350860125269734776835706319998126932434578043055227409281588612984018091383059766138922330022055995070848238700892073784700276201717962714793918423998717965307215876100622198480951034966832470036676432489868843611398182340500492812245045490103046669276860163011341682528926046233786438346932476779382472611559621089775672675709689 [0xf7e54e7f4327a45f63c07a559a32e8d7d2cfd4f2dffcd7af08e0f63251451983000000000000000000000000000000000000000000000000000000000000f0f000000000000000005cfbd765ce33f34ea20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f5073a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9] vs 46813745598827674767692165924842801974770606093098512579335913208855850916439256961360726372076546744205740461193913990350946466833431394623724028518959004073435773078301075342461819622058537951172415275209737612013454654676737733904112589532940753146007209435090862155913380316949363917651364605172761177802864569067691889011154051760420464800505 [0xc3e929645e4f98901d03bda276e84aaad61db03ceadb543fc53aac1a0b8f613f000000000000000000000000000000000000000000000000000000000000f0f000000000000000005cfbd765ce33f34ea20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f5073a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9]) cdi_type: Attestation
  
   HardwareRevisionSecret act: 0x3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9, exp: 0x3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9
   RomDigest act: 0xa20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f507, exp: 0xa20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f507
   HealthMeasurement act: 0x5cfbd765ce33f34e, exp: 0x5cfbd765ce33f34e