KEYMGR Simulation Results

Saturday July 13 2024 23:02:33 UTC

GitHub Revision: `d51405297e`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 101086804359139103922259090811397817605469534164678958852189348539757618502888

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	35.690s	2.678ms	50	50	100.00
V1	random	keymgr_random	1.522m	5.050ms	49	50	98.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.190s	64.838us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.250s	14.721us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	35.550s	12.727ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	10.520s	1.788ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.210s	51.057us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.250s	14.721us	20	20	100.00
		keymgr_csr_aliasing	10.520s	1.788ms	5	5	100.00
V1		TOTAL			154	155	99.35
V2	cfgen_during_op	keymgr_cfg_regwen	1.372m	3.014ms	50	50	100.00
V2	sideload	keymgr_sideload	42.570s	5.092ms	50	50	100.00
		keymgr_sideload_kmac	51.850s	7.540ms	50	50	100.00
		keymgr_sideload_aes	44.020s	6.984ms	50	50	100.00
		keymgr_sideload_otbn	1.144m	13.552ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	23.100s	961.328us	50	50	100.00
V2	lc_disable	keymgr_lc_disable	21.470s	706.551us	50	50	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	9.450s	266.026us	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	46.510s	23.453ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	26.340s	2.009ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	15.040s	6.940ms	50	50	100.00
V2	stress_all	keymgr_stress_all	9.731m	89.512ms	48	50	96.00
V2	intr_test	keymgr_intr_test	0.940s	19.139us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.020s	19.386us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	3.730s	314.894us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	3.730s	314.894us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.190s	64.838us	5	5	100.00
		keymgr_csr_rw	1.250s	14.721us	20	20	100.00
		keymgr_csr_aliasing	10.520s	1.788ms	5	5	100.00
		keymgr_same_csr_outstanding	4.140s	121.709us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.190s	64.838us	5	5	100.00
		keymgr_csr_rw	1.250s	14.721us	20	20	100.00
		keymgr_csr_aliasing	10.520s	1.788ms	5	5	100.00
		keymgr_same_csr_outstanding	4.140s	121.709us	20	20	100.00
V2		TOTAL			738	740	99.73
V2S	sec_cm_additional_check	keymgr_sec_cm	22.920s	1.405ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	22.920s	1.405ms	5	5	100.00
		keymgr_tl_intg_err	10.670s	1.073ms	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	4.630s	615.727us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	4.630s	615.727us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	4.630s	615.727us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	4.630s	615.727us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	13.270s	380.588us	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	22.920s	1.405ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	22.920s	1.405ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	10.670s	1.073ms	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	4.630s	615.727us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.372m	3.014ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	1.522m	5.050ms	49	50	98.00
		keymgr_csr_rw	1.250s	14.721us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	1.522m	5.050ms	49	50	98.00
		keymgr_csr_rw	1.250s	14.721us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	1.522m	5.050ms	49	50	98.00
		keymgr_csr_rw	1.250s	14.721us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	21.470s	706.551us	50	50	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	26.340s	2.009ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	26.340s	2.009ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	1.522m	5.050ms	49	50	98.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	35.000s	5.421ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	22.920s	1.405ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	22.920s	1.405ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	22.920s	1.405ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	20.920s	10.496ms	49	50	98.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	21.470s	706.551us	50	50	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	22.920s	1.405ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	22.920s	1.405ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	22.920s	1.405ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	20.920s	10.496ms	49	50	98.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	20.920s	10.496ms	49	50	98.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	22.920s	1.405ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	20.920s	10.496ms	49	50	98.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	22.920s	1.405ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	20.920s	10.496ms	49	50	98.00
V2S		TOTAL			164	165	99.39
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	32.460s	3.807ms	21	50	42.00
V3		TOTAL			21	50	42.00
		TOTAL			1077	1110	97.03

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	6	85.71
V2	16	16	15	93.75
V2S	6	6	5	83.33
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.71	99.04	97.95	98.38	100.00	99.02	98.41	91.19

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 28 failures:
- Test keymgr_stress_all_with_rand_reset has 28 failures.
  - 0.keymgr_stress_all_with_rand_reset.103211239572333444175300383482384120881279249468064270019619883344408821835821
    Line 471, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 437657213 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10005 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 437657213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.keymgr_stress_all_with_rand_reset.113913325844030321581360015401191866066289284322931822963195147381769652554130
    Line 1043, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/2.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1577100025 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1577100025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 26 more failures.

UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 3 failures:

Test keymgr_random has 1 failures.

19.keymgr_random.77128929109543391124632639052216887707143321252594047069160948484961298764903
Line 389, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/19.keymgr_random/latest/run.log

  UVM_ERROR @  25841695 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @  25841695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_stress_all has 2 failures.

28.keymgr_stress_all.33614289695165420687313841929379890238297464874152865955104305612830073111384
Line 4543, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/28.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 2252146622 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @ 2252146622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

38.keymgr_stress_all.44241883455837272039407557201763522392129933743962090177255480719159846985820
Line 1858, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/38.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 162765259 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @ 162765259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (keymgr_custom_cm_vseq.sv:45) [keymgr_custom_cm_vseq] wait timeout occurred! has 1 failures:
- Test keymgr_custom_cm has 1 failures.
  - 45.keymgr_custom_cm.61242374071485101129833071375239877295716211246856715551142340740349032804977
    Line 430, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/45.keymgr_custom_cm/latest/run.log
```
  UVM_FATAL @ 10495760074 ps: (keymgr_custom_cm_vseq.sv:45) [uvm_test_top.env.virtual_sequencer.keymgr_custom_cm_vseq] wait timeout occurred!
  UVM_INFO @ 10495760074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data !=gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share0_output_*` has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 48.keymgr_stress_all_with_rand_reset.109456363394943264467021782167089796160776113093254750758101081142865307953179
    Line 1729, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/48.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 282164075 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share0_output_0
  UVM_INFO @ 282164075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```