c04cc5d074
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | keymgr_smoke | 36.350s | 1.531ms | 50 | 50 | 100.00 |
V1 | random | keymgr_random | 1.338m | 20.427ms | 50 | 50 | 100.00 |
V1 | csr_hw_reset | keymgr_csr_hw_reset | 1.480s | 141.359us | 5 | 5 | 100.00 |
V1 | csr_rw | keymgr_csr_rw | 1.530s | 50.802us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | keymgr_csr_bit_bash | 16.620s | 651.326us | 5 | 5 | 100.00 |
V1 | csr_aliasing | keymgr_csr_aliasing | 10.200s | 1.009ms | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | keymgr_csr_mem_rw_with_rand_reset | 2.380s | 71.813us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | keymgr_csr_rw | 1.530s | 50.802us | 20 | 20 | 100.00 |
keymgr_csr_aliasing | 10.200s | 1.009ms | 5 | 5 | 100.00 | ||
V1 | TOTAL | 155 | 155 | 100.00 | |||
V2 | cfgen_during_op | keymgr_cfg_regwen | 1.604m | 1.916ms | 48 | 50 | 96.00 |
V2 | sideload | keymgr_sideload | 44.740s | 2.222ms | 50 | 50 | 100.00 |
keymgr_sideload_kmac | 54.190s | 5.684ms | 50 | 50 | 100.00 | ||
keymgr_sideload_aes | 52.800s | 4.331ms | 50 | 50 | 100.00 | ||
keymgr_sideload_otbn | 45.810s | 1.508ms | 50 | 50 | 100.00 | ||
V2 | direct_to_disabled_state | keymgr_direct_to_disabled | 46.580s | 28.220ms | 50 | 50 | 100.00 |
V2 | lc_disable | keymgr_lc_disable | 12.400s | 847.842us | 50 | 50 | 100.00 |
V2 | kmac_error_response | keymgr_kmac_rsp_err | 10.290s | 2.593ms | 50 | 50 | 100.00 |
V2 | invalid_sw_input | keymgr_sw_invalid_input | 1.126m | 11.439ms | 50 | 50 | 100.00 |
V2 | invalid_hw_input | keymgr_hwsw_invalid_input | 1.259m | 12.829ms | 50 | 50 | 100.00 |
V2 | sync_async_fault_cross | keymgr_sync_async_fault_cross | 10.950s | 1.067ms | 50 | 50 | 100.00 |
V2 | stress_all | keymgr_stress_all | 9.922m | 50.350ms | 48 | 50 | 96.00 |
V2 | intr_test | keymgr_intr_test | 0.950s | 18.968us | 50 | 50 | 100.00 |
V2 | alert_test | keymgr_alert_test | 0.990s | 15.546us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | keymgr_tl_errors | 3.690s | 690.912us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | keymgr_tl_errors | 3.690s | 690.912us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | keymgr_csr_hw_reset | 1.480s | 141.359us | 5 | 5 | 100.00 |
keymgr_csr_rw | 1.530s | 50.802us | 20 | 20 | 100.00 | ||
keymgr_csr_aliasing | 10.200s | 1.009ms | 5 | 5 | 100.00 | ||
keymgr_same_csr_outstanding | 3.650s | 433.370us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | keymgr_csr_hw_reset | 1.480s | 141.359us | 5 | 5 | 100.00 |
keymgr_csr_rw | 1.530s | 50.802us | 20 | 20 | 100.00 | ||
keymgr_csr_aliasing | 10.200s | 1.009ms | 5 | 5 | 100.00 | ||
keymgr_same_csr_outstanding | 3.650s | 433.370us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 736 | 740 | 99.46 | |||
V2S | sec_cm_additional_check | keymgr_sec_cm | 10.700s | 327.455us | 5 | 5 | 100.00 |
V2S | tl_intg_err | keymgr_sec_cm | 10.700s | 327.455us | 5 | 5 | 100.00 |
keymgr_tl_intg_err | 10.390s | 502.270us | 20 | 20 | 100.00 | ||
V2S | shadow_reg_update_error | keymgr_shadow_reg_errors | 6.560s | 309.021us | 20 | 20 | 100.00 |
V2S | shadow_reg_read_clear_staged_value | keymgr_shadow_reg_errors | 6.560s | 309.021us | 20 | 20 | 100.00 |
V2S | shadow_reg_storage_error | keymgr_shadow_reg_errors | 6.560s | 309.021us | 20 | 20 | 100.00 |
V2S | shadowed_reset_glitch | keymgr_shadow_reg_errors | 6.560s | 309.021us | 20 | 20 | 100.00 |
V2S | shadow_reg_update_error_with_csr_rw | keymgr_shadow_reg_errors_with_csr_rw | 13.940s | 1.461ms | 20 | 20 | 100.00 |
V2S | prim_count_check | keymgr_sec_cm | 10.700s | 327.455us | 5 | 5 | 100.00 |
V2S | prim_fsm_check | keymgr_sec_cm | 10.700s | 327.455us | 5 | 5 | 100.00 |
V2S | sec_cm_bus_integrity | keymgr_tl_intg_err | 10.390s | 502.270us | 20 | 20 | 100.00 |
V2S | sec_cm_config_shadow | keymgr_shadow_reg_errors | 6.560s | 309.021us | 20 | 20 | 100.00 |
V2S | sec_cm_op_config_regwen | keymgr_cfg_regwen | 1.604m | 1.916ms | 48 | 50 | 96.00 |
V2S | sec_cm_reseed_config_regwen | keymgr_random | 1.338m | 20.427ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.530s | 50.802us | 20 | 20 | 100.00 | ||
V2S | sec_cm_sw_binding_config_regwen | keymgr_random | 1.338m | 20.427ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.530s | 50.802us | 20 | 20 | 100.00 | ||
V2S | sec_cm_max_key_ver_config_regwen | keymgr_random | 1.338m | 20.427ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.530s | 50.802us | 20 | 20 | 100.00 | ||
V2S | sec_cm_lc_ctrl_intersig_mubi | keymgr_lc_disable | 12.400s | 847.842us | 50 | 50 | 100.00 |
V2S | sec_cm_constants_consistency | keymgr_hwsw_invalid_input | 1.259m | 12.829ms | 50 | 50 | 100.00 |
V2S | sec_cm_intersig_consistency | keymgr_hwsw_invalid_input | 1.259m | 12.829ms | 50 | 50 | 100.00 |
V2S | sec_cm_hw_key_sw_noaccess | keymgr_random | 1.338m | 20.427ms | 50 | 50 | 100.00 |
V2S | sec_cm_output_keys_ctrl_redun | keymgr_sideload_protect | 22.090s | 859.449us | 50 | 50 | 100.00 |
V2S | sec_cm_ctrl_fsm_sparse | keymgr_sec_cm | 10.700s | 327.455us | 5 | 5 | 100.00 |
V2S | sec_cm_data_fsm_sparse | keymgr_sec_cm | 10.700s | 327.455us | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_fsm_local_esc | keymgr_sec_cm | 10.700s | 327.455us | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_fsm_consistency | keymgr_custom_cm | 30.120s | 1.545ms | 50 | 50 | 100.00 |
V2S | sec_cm_ctrl_fsm_global_esc | keymgr_lc_disable | 12.400s | 847.842us | 50 | 50 | 100.00 |
V2S | sec_cm_ctrl_ctr_redun | keymgr_sec_cm | 10.700s | 327.455us | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_fsm_sparse | keymgr_sec_cm | 10.700s | 327.455us | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_ctr_redun | keymgr_sec_cm | 10.700s | 327.455us | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_cmd_ctrl_consistency | keymgr_custom_cm | 30.120s | 1.545ms | 50 | 50 | 100.00 |
V2S | sec_cm_kmac_if_done_ctrl_consistency | keymgr_custom_cm | 30.120s | 1.545ms | 50 | 50 | 100.00 |
V2S | sec_cm_reseed_ctr_redun | keymgr_sec_cm | 10.700s | 327.455us | 5 | 5 | 100.00 |
V2S | sec_cm_side_load_sel_ctrl_consistency | keymgr_custom_cm | 30.120s | 1.545ms | 50 | 50 | 100.00 |
V2S | sec_cm_sideload_ctrl_fsm_sparse | keymgr_sec_cm | 10.700s | 327.455us | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_key_integrity | keymgr_custom_cm | 30.120s | 1.545ms | 50 | 50 | 100.00 |
V2S | TOTAL | 165 | 165 | 100.00 | |||
V3 | stress_all_with_rand_reset | keymgr_stress_all_with_rand_reset | 26.920s | 5.341ms | 28 | 50 | 56.00 |
V3 | TOTAL | 28 | 50 | 56.00 | |||
TOTAL | 1084 | 1110 | 97.66 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 7 | 7 | 7 | 100.00 |
V2 | 16 | 16 | 14 | 87.50 |
V2S | 6 | 6 | 6 | 100.00 |
V3 | 1 | 1 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
97.75 | 99.04 | 98.07 | 98.46 | 100.00 | 99.02 | 98.41 | 91.29 |
UVM_ERROR (cip_base_vseq.sv:825) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
has 21 failures:
0.keymgr_stress_all_with_rand_reset.113270119378801420588338421698911611499963407255718793795992219437361974928610
Line 614, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 391152100 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 391152100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.keymgr_stress_all_with_rand_reset.93733528882022682541772083383450243742494438867398660681758885906718727264728
Line 405, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/3.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 128396969 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 128396969 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 19 more failures.
UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:*
has 2 failures:
Test keymgr_stress_all has 1 failures.
37.keymgr_stress_all.97917417984947593955215968430294643836257924264304314301797400198980258448482
Line 1197, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/37.keymgr_stress_all/latest/run.log
UVM_ERROR @ 2256504441 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
UVM_INFO @ 2256504441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test keymgr_cfg_regwen has 1 failures.
49.keymgr_cfg_regwen.92257854865661742245566586069153167166107650429949738241957051184020469151919
Line 330, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/49.keymgr_cfg_regwen/latest/run.log
UVM_ERROR @ 20603383 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
UVM_INFO @ 20603383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data !=
gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share1_output_*` has 1 failures:
12.keymgr_stress_all.60625265171455543814116014843347562276095703425173127248887021677388441618093
Line 2571, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/12.keymgr_stress_all/latest/run.log
UVM_ERROR @ 7666399224 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share1_output_3
UVM_INFO @ 7666399224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:749) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
has 1 failures:
38.keymgr_stress_all_with_rand_reset.59944345185546530156454221239683683767578426146858870694447310273465081955204
Line 845, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/38.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2430526660 ps: (cip_base_vseq.sv:749) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 2430526660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:794) [scoreboard] Check failed item.d_data ==
gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.start` has 1 failures:
42.keymgr_cfg_regwen.45083079216377674609687283639095601530554206078422788295746785361170417675659
Line 315, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/42.keymgr_cfg_regwen/latest/run.log
UVM_ERROR @ 13797394 ps: (keymgr_scoreboard.sv:794) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 1 [0x1]) reg name: keymgr_reg_block.start
UVM_INFO @ 13797394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---