cf38c1d296| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | kmac_smoke | 1.868m | 13.058ms | 49 | 50 | 98.00 |
| V1 | csr_hw_reset | kmac_csr_hw_reset | 1.110s | 236.472us | 5 | 5 | 100.00 |
| V1 | csr_rw | kmac_csr_rw | 1.260s | 519.510us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | kmac_csr_bit_bash | 23.920s | 2.632ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | kmac_csr_aliasing | 11.240s | 1.079ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | kmac_csr_mem_rw_with_rand_reset | 2.230s | 102.155us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | kmac_csr_rw | 1.260s | 519.510us | 20 | 20 | 100.00 |
| kmac_csr_aliasing | 11.240s | 1.079ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | kmac_mem_walk | 0.760s | 39.811us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | kmac_mem_partial_access | 1.450s | 104.445us | 5 | 5 | 100.00 |
| V1 | TOTAL | 114 | 115 | 99.13 | |||
| V2 | long_msg_and_output | kmac_long_msg_and_output | 53.211m | 338.172ms | 49 | 50 | 98.00 |
| V2 | burst_write | kmac_burst_write | 27.166m | 32.483ms | 47 | 50 | 94.00 |
| V2 | test_vectors | kmac_test_vectors_sha3_224 | 41.482m | 607.265ms | 49 | 50 | 98.00 |
| kmac_test_vectors_sha3_256 | 45.749m | 1.540s | 49 | 50 | 98.00 | ||
| kmac_test_vectors_sha3_384 | 34.572m | 987.716ms | 50 | 50 | 100.00 | ||
| kmac_test_vectors_sha3_512 | 25.077m | 877.925ms | 50 | 50 | 100.00 | ||
| kmac_test_vectors_shake_128 | 1.746h | 270.202ms | 50 | 50 | 100.00 | ||
| kmac_test_vectors_shake_256 | 1.741h | 617.099ms | 49 | 50 | 98.00 | ||
| kmac_test_vectors_kmac | 7.320s | 435.053us | 49 | 50 | 98.00 | ||
| kmac_test_vectors_kmac_xof | 7.240s | 479.235us | 50 | 50 | 100.00 | ||
| V2 | sideload | kmac_sideload | 8.647m | 85.890ms | 48 | 50 | 96.00 |
| V2 | app | kmac_app | 6.787m | 35.944ms | 49 | 50 | 98.00 |
| V2 | app_with_partial_data | kmac_app_with_partial_data | 6.815m | 19.374ms | 10 | 10 | 100.00 |
| V2 | entropy_refresh | kmac_entropy_refresh | 7.234m | 163.663ms | 50 | 50 | 100.00 |
| V2 | error | kmac_error | 9.095m | 85.194ms | 48 | 50 | 96.00 |
| V2 | key_error | kmac_key_error | 8.330s | 6.676ms | 49 | 50 | 98.00 |
| V2 | edn_timeout_error | kmac_edn_timeout_error | 57.590s | 13.253ms | 20 | 20 | 100.00 |
| V2 | entropy_mode_error | kmac_entropy_mode_error | 26.540s | 4.257ms | 20 | 20 | 100.00 |
| V2 | entropy_ready_error | kmac_entropy_ready_error | 1.147m | 5.763ms | 10 | 10 | 100.00 |
| V2 | lc_escalation | kmac_lc_escalation | 43.410s | 3.374ms | 50 | 50 | 100.00 |
| V2 | stress_all | kmac_stress_all | 39.851m | 87.615ms | 47 | 50 | 94.00 |
| V2 | intr_test | kmac_intr_test | 0.870s | 53.129us | 50 | 50 | 100.00 |
| V2 | alert_test | kmac_alert_test | 0.890s | 74.624us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | kmac_tl_errors | 2.990s | 672.107us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | kmac_tl_errors | 2.990s | 672.107us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | kmac_csr_hw_reset | 1.110s | 236.472us | 5 | 5 | 100.00 |
| kmac_csr_rw | 1.260s | 519.510us | 20 | 20 | 100.00 | ||
| kmac_csr_aliasing | 11.240s | 1.079ms | 5 | 5 | 100.00 | ||
| kmac_same_csr_outstanding | 2.920s | 660.109us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | kmac_csr_hw_reset | 1.110s | 236.472us | 5 | 5 | 100.00 |
| kmac_csr_rw | 1.260s | 519.510us | 20 | 20 | 100.00 | ||
| kmac_csr_aliasing | 11.240s | 1.079ms | 5 | 5 | 100.00 | ||
| kmac_same_csr_outstanding | 2.920s | 660.109us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1033 | 1050 | 98.38 | |||
| V2S | shadow_reg_update_error | kmac_shadow_reg_errors | 1.570s | 104.575us | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | kmac_shadow_reg_errors | 1.570s | 104.575us | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | kmac_shadow_reg_errors | 1.570s | 104.575us | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | kmac_shadow_reg_errors | 1.570s | 104.575us | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | kmac_shadow_reg_errors_with_csr_rw | 3.700s | 2.166ms | 19 | 20 | 95.00 |
| V2S | tl_intg_err | kmac_sec_cm | 1.947m | 7.534ms | 4 | 5 | 80.00 |
| kmac_tl_intg_err | 5.850s | 3.582ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | kmac_tl_intg_err | 5.850s | 3.582ms | 20 | 20 | 100.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | kmac_lc_escalation | 43.410s | 3.374ms | 50 | 50 | 100.00 |
| V2S | sec_cm_sw_key_key_masking | kmac_smoke | 1.868m | 13.058ms | 49 | 50 | 98.00 |
| V2S | sec_cm_key_sideload | kmac_sideload | 8.647m | 85.890ms | 48 | 50 | 96.00 |
| V2S | sec_cm_cfg_shadowed_config_shadow | kmac_shadow_reg_errors | 1.570s | 104.575us | 20 | 20 | 100.00 |
| V2S | sec_cm_fsm_sparse | kmac_sec_cm | 1.947m | 7.534ms | 4 | 5 | 80.00 |
| V2S | sec_cm_ctr_redun | kmac_sec_cm | 1.947m | 7.534ms | 4 | 5 | 80.00 |
| V2S | sec_cm_packer_ctr_redun | kmac_sec_cm | 1.947m | 7.534ms | 4 | 5 | 80.00 |
| V2S | sec_cm_cfg_shadowed_config_regwen | kmac_smoke | 1.868m | 13.058ms | 49 | 50 | 98.00 |
| V2S | sec_cm_fsm_global_esc | kmac_lc_escalation | 43.410s | 3.374ms | 50 | 50 | 100.00 |
| V2S | sec_cm_fsm_local_esc | kmac_sec_cm | 1.947m | 7.534ms | 4 | 5 | 80.00 |
| V2S | sec_cm_absorbed_ctrl_mubi | kmac_mubi | 6.136m | 5.177ms | 10 | 10 | 100.00 |
| V2S | sec_cm_sw_cmd_ctrl_sparse | kmac_smoke | 1.868m | 13.058ms | 49 | 50 | 98.00 |
| V2S | TOTAL | 73 | 75 | 97.33 | |||
| V3 | throughput | kmac_throughput | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | kmac_stress_all_with_rand_reset | 41.060m | 78.369ms | 35 | 50 | 70.00 |
| V3 | TOTAL | 35 | 50 | 70.00 | |||
| TOTAL | 1255 | 1290 | 97.29 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 25 | 25 | 14 | 56.00 |
| V2S | 5 | 5 | 3 | 60.00 |
| V3 | 2 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.01 | 98.38 | 93.15 | 99.93 | 94.55 | 96.04 | 98.89 | 98.17 |
UVM_ERROR (kmac_scoreboard.sv:1176) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 12 failures:
2.kmac_stress_all_with_rand_reset.113316108007573493883351631341336971674388134438266037815263307674835401468473
Line 292, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 596896510 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483760 [0x80000070]) reg name: kmac_reg_block.err_code
UVM_INFO @ 596896510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.kmac_stress_all_with_rand_reset.29734426624888778075634323627445252466305460971893478236620282271174526589881
Line 383, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 20160369815 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483688 [0x80000028]) reg name: kmac_reg_block.err_code
UVM_INFO @ 20160369815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 10 more failures.
Exit reason: Error: User command failed Job returned non-zero exit code has 7 failures:
Test kmac_sec_cm has 1 failures.
2.kmac_sec_cm.6486443980005618149022887169440556106884022810012026673530285468301356381524
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_sec_cm/latest/run.log
[make]: simulate
cd /workspace/2.kmac_sec_cm/latest && /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802346836 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sec_cm.3802346836 +enable_masking=1 +sw_key_masked=0
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 10 12:50 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test kmac_sideload has 1 failures.
15.kmac_sideload.53492062659503712057578396478312629528314454063042414495046366419664059078028
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/15.kmac_sideload/latest/run.log
[make]: simulate
cd /workspace/15.kmac_sideload/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098725260 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_sideload.4098725260 +enable_masking=1 +sw_key_masked=0
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 10 12:51 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test kmac_long_msg_and_output has 1 failures.
18.kmac_long_msg_and_output.48759265220981495779385817066595682122496772877791621726998303773455047297516
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/18.kmac_long_msg_and_output/latest/run.log
[make]: simulate
cd /workspace/18.kmac_long_msg_and_output/latest && /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665581036 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_long_msg_and_output.2665581036 +enable_masking=1 +sw_key_masked=0
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 10 12:51 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test kmac_stress_all has 1 failures.
25.kmac_stress_all.28158885246513909561057365992376774754947527031007611877026775071923171677817
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/25.kmac_stress_all/latest/run.log
[make]: simulate
cd /workspace/25.kmac_stress_all/latest && /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310278265 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_stress_all.3310278265 +enable_masking=1 +sw_key_masked=0
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 10 12:51 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test kmac_test_vectors_kmac has 1 failures.
27.kmac_test_vectors_kmac.105819545729981333037191095696782232077494302704963184860443150714178764566499
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/27.kmac_test_vectors_kmac/latest/run.log
[make]: simulate
cd /workspace/27.kmac_test_vectors_kmac/latest && /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996962275 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_kmac.996962275 +enable_masking=1 +sw_key_masked=0
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 10 12:51 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 2 more tests.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 5 failures:
Test kmac_sideload has 1 failures.
13.kmac_sideload.8003155176543398874755482106534136493447346930030206246485491012364459209032
Line 444, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/13.kmac_sideload/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_burst_write has 3 failures.
21.kmac_burst_write.27877979667151839515576567615860865053708924381382069721454830554690320519626
Line 372, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/21.kmac_burst_write/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
39.kmac_burst_write.87355788083684009565415221509843318740660594897019706328973761944945169464526
Line 366, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/39.kmac_burst_write/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test kmac_error has 1 failures.
21.kmac_error.42907694125828198311683973624438150377185129964757695402322637644978419516586
Line 387, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/21.kmac_error/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 4 failures:
Test kmac_error has 1 failures.
6.kmac_error.103136865226276311033206251932611820751840792585815050743241303118729510182263
Line 310, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_error/latest/run.log
UVM_FATAL @ 10309560751 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
UVM_INFO @ 10309560751 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_stress_all has 2 failures.
20.kmac_stress_all.1277481550808271263107895127355304032138007767379524853503598529946856052759
Line 393, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/20.kmac_stress_all/latest/run.log
UVM_FATAL @ 39146803573 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
UVM_INFO @ 39146803573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
21.kmac_stress_all.103265040829696817813008842683587315288288707367026156475479371766163004206823
Line 400, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/21.kmac_stress_all/latest/run.log
UVM_FATAL @ 42004597693 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
UVM_INFO @ 42004597693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_stress_all_with_rand_reset has 1 failures.
41.kmac_stress_all_with_rand_reset.66154191339305767866207528451892135652146700326343846041098981659077918142786
Line 1214, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/41.kmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 199733233703 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
UVM_INFO @ 199733233703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 2 failures:
Test kmac_test_vectors_sha3_256 has 1 failures.
15.kmac_test_vectors_sha3_256.65012054710323634624154806006813077210682778096226828545587662244760518329831
Line 277, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/15.kmac_test_vectors_sha3_256/latest/run.log
UVM_ERROR @ 90210242 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 90210242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_test_vectors_shake_256 has 1 failures.
36.kmac_test_vectors_shake_256.16081870692957385085329936767563914718965351478359869810113971238928525261307
Line 277, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/36.kmac_test_vectors_shake_256/latest/run.log
UVM_ERROR @ 367603202 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 367603202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (kmac_scoreboard.sv:1520) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 2 failures:
Test kmac_app has 1 failures.
23.kmac_app.40078272290902811899806298754972436248297888071137545583988248416009522324974
Line 293, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/23.kmac_app/latest/run.log
UVM_FATAL @ 4643596874 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (87 [0x57] vs 186 [0xba]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 4643596874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_stress_all_with_rand_reset has 1 failures.
31.kmac_stress_all_with_rand_reset.80375030310227837160880706489679818648651888861617715734165502925926436309098
Line 527, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/31.kmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 9666730232 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (243 [0xf3] vs 148 [0x94]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 9666730232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job kmac_masked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
15.kmac_test_vectors_sha3_224.40799661601361190390790113396309323664581767193803714485650881563701803222384
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/15.kmac_test_vectors_sha3_224/latest/run.log
Job ID: smart:5dad8e90-c5a4-4d41-a698-9d0fb506f25f
UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_* reset value: * has 1 failures:
17.kmac_shadow_reg_errors_with_csr_rw.81101493721005058312163711143483135031028579170264853035112828164003495518687
Line 280, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/17.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
UVM_ERROR @ 127916923 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (2303203517 [0x894818bd] vs 993689866 [0x3b3a810a]) Regname: kmac_reg_block.prefix_0 reset value: 0x0
UVM_INFO @ 127916923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (kmac_test_vectors_base_vseq.sv:125) [kmac_test_vectors_kmac_xof_vseq] Check failed exp_digest[i] == act_digest[i] (* [*] vs * [*]) Mismatch between exp_digest[*] and act_digest[*] has 1 failures:
39.kmac_stress_all_with_rand_reset.38302813253923767620450665335948074661702490237897976532857813927443328786234
Line 571, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/39.kmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 20501759115 ps: (kmac_test_vectors_base_vseq.sv:125) [uvm_test_top.env.virtual_sequencer.kmac_test_vectors_kmac_xof_vseq] Check failed exp_digest[i] == act_digest[i] (49 [0x31] vs 77 [0x4d]) Mismatch between exp_digest[52] and act_digest[52]
UVM_INFO @ 20501759115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---