KMAC/MASKED Simulation Results

Sunday January 14 2024 20:02:50 UTC

GitHub Revision: 5f48fbc0e7

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 17974844803940076144755676589184454804069451770040436570888369542024131598097

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.871m	9.902ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.260s	94.619us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.240s	108.127us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	24.330s	3.100ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.950s	317.228us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.090s	37.536us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.240s	108.127us	20	20	100.00
		kmac_csr_aliasing	9.950s	317.228us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.790s	13.566us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.530s	96.163us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	56.535m	333.854ms	50	50	100.00
V2	burst_write	kmac_burst_write	26.422m	43.123ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	46.552m	1.293s	48	50	96.00
		kmac_test_vectors_sha3_256	42.880m	997.345ms	50	50	100.00
		kmac_test_vectors_sha3_384	33.628m	282.878ms	50	50	100.00
		kmac_test_vectors_sha3_512	27.287m	211.841ms	50	50	100.00
		kmac_test_vectors_shake_128	1.974h	3.807s	49	50	98.00
		kmac_test_vectors_shake_256	1.757h	2.155s	50	50	100.00
		kmac_test_vectors_kmac	7.790s	481.473us	50	50	100.00
		kmac_test_vectors_kmac_xof	7.520s	2.266ms	50	50	100.00
V2	sideload	kmac_sideload	10.072m	46.491ms	50	50	100.00
V2	app	kmac_app	7.039m	14.150ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.751m	25.455ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	7.520m	31.208ms	50	50	100.00
V2	error	kmac_error	10.022m	22.911ms	47	50	94.00
V2	key_error	kmac_key_error	8.580s	4.870ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	49.910s	5.624ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	47.710s	1.400ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.310m	7.861ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	34.560s	15.778ms	50	50	100.00
V2	stress_all	kmac_stress_all	59.675m	101.462ms	47	50	94.00
V2	intr_test	kmac_intr_test	0.930s	14.056us	50	50	100.00
V2	alert_test	kmac_alert_test	0.960s	62.117us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.460s	662.078us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.460s	662.078us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.260s	94.619us	5	5	100.00
		kmac_csr_rw	1.240s	108.127us	20	20	100.00
		kmac_csr_aliasing	9.950s	317.228us	5	5	100.00
		kmac_same_csr_outstanding	2.910s	505.216us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.260s	94.619us	5	5	100.00
		kmac_csr_rw	1.240s	108.127us	20	20	100.00
		kmac_csr_aliasing	9.950s	317.228us	5	5	100.00
		kmac_same_csr_outstanding	2.910s	505.216us	20	20	100.00
V2		TOTAL			1040	1050	99.05
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.500s	56.738us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.500s	56.738us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.500s	56.738us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.500s	56.738us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.340s	225.731us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.712m	7.959ms	5	5	100.00
		kmac_tl_intg_err	6.650s	273.481us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	6.650s	273.481us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	34.560s	15.778ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.871m	9.902ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	10.072m	46.491ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.500s	56.738us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.712m	7.959ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.712m	7.959ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.712m	7.959ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.871m	9.902ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	34.560s	15.778ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.712m	7.959ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	7.145m	53.186ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.871m	9.902ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.263h	1.173s	34	50	68.00
V3		TOTAL			34	50	68.00
		TOTAL			1264	1290	97.98

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	20	80.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.16	98.38	93.15	99.93	95.45	96.04	98.89	98.31

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1176) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 11 failures:

  • Test kmac_stress_all_with_rand_reset has 11 failures.

    • 1.kmac_stress_all_with_rand_reset.48454433886815653934340536136217307104335683107339638200297168383251341862702
      Line 757, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 218982283401 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483752 [0x80000068]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 218982283401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 6.kmac_stress_all_with_rand_reset.1837182558056639491895336852541525591783017633735747492955849428696985436879
      Line 579, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 22426682137 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483704 [0x80000038]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 22426682137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 9 more failures.

• UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 10 failures:

  • Test kmac_error has 3 failures.

    • 0.kmac_error.82261758064991640307045767428756042176823525648033662276188725091373857843246
      Line 371, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_error/latest/run.log

        UVM_FATAL @ 10054180692 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
        UVM_INFO @ 10054180692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.kmac_error.13085942587354518168217049036373646936432176351172857618957099437864351339894
      Line 351, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_error/latest/run.log

        UVM_FATAL @ 10072375850 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
        UVM_INFO @ 10072375850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

  • Test kmac_stress_all_with_rand_reset has 5 failures.

    • 14.kmac_stress_all_with_rand_reset.86221015762012645264631712595792002803279552531033718160101318893012020726555
      Line 697, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 127207201577 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
        UVM_INFO @ 127207201577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 22.kmac_stress_all_with_rand_reset.42221058694850742037431120216114549941795394875334177637735352289305749221385
      Line 1770, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/22.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 513003069804 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
        UVM_INFO @ 513003069804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 3 more failures.

  • Test kmac_stress_all has 2 failures.

    • 24.kmac_stress_all.68787756222480207834428253986740585151865478236568170780894420030416164857260
      Line 598, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/24.kmac_stress_all/latest/run.log

        UVM_FATAL @ 551971036347 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
        UVM_INFO @ 551971036347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 49.kmac_stress_all.24756918594801324443720665672710113653881994982673623265638026548757533672161
      Line 717, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/49.kmac_stress_all/latest/run.log

        UVM_FATAL @ 563760623259 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
        UVM_INFO @ 563760623259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 2 failures:

  • Test kmac_test_vectors_sha3_224 has 2 failures.

    • 4.kmac_test_vectors_sha3_224.37867151777948553047265750392796591068590593489242881347610340821542031453412
      Line 277, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_224/latest/run.log

        UVM_ERROR @  64426421 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
        UVM_INFO @  64426421 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 26.kmac_test_vectors_sha3_224.75852672174015125792031160573892362400261259688585497647778939972676605858645
      Line 277, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/26.kmac_test_vectors_sha3_224/latest/run.log

        UVM_ERROR @  40839980 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
        UVM_INFO @  40839980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job kmac_masked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:

  • Test kmac_test_vectors_shake_128 has 1 failures.

    • 22.kmac_test_vectors_shake_128.45898161970913149507877214497522536805286077944082955566591364270387836973992
      Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/22.kmac_test_vectors_shake_128/latest/run.log

        Job ID: smart:6e36463a-a369-485b-9cf0-16e96ab378fb
      

• UVM_FATAL (kmac_scoreboard.sv:1520) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 1 failures:

  • Test kmac_stress_all has 1 failures.

    • 30.kmac_stress_all.55386319675177686393113321446246202626804757619626500741869441537307032835566
      Line 438, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/30.kmac_stress_all/latest/run.log

        UVM_FATAL @ 7693237399 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (28 [0x1c] vs 246 [0xf6]) Mismatch between unmasked_digest[0] and dpi_digest[0]
        UVM_INFO @ 7693237399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test kmac_burst_write has 1 failures.

    • 34.kmac_burst_write.29436971953978801954588677374176689818326471535776172824784976575022035907642
      Line 444, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/34.kmac_burst_write/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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