KMAC/MASKED Simulation Results

Tuesday March 05 2024 20:02:48 UTC

GitHub Revision: `c30684b3ca`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 61875946985821051720030118255902427822651914203242934898647746371735217685454

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.634m	28.076ms	49	50	98.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.170s	94.285us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.380s	457.936us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	20.720s	8.051ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.190s	524.311us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.930s	1.320ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.380s	457.936us	20	20	100.00
		kmac_csr_aliasing	10.190s	524.311us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.880s	184.983us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.490s	44.840us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	long_msg_and_output	kmac_long_msg_and_output	53.300m	114.463ms	49	50	98.00
V2	burst_write	kmac_burst_write	28.217m	14.491ms	48	50	96.00
V2	test_vectors	kmac_test_vectors_sha3_224	42.615m	205.499ms	49	50	98.00
		kmac_test_vectors_sha3_256	50.345m	1.821s	48	50	96.00
		kmac_test_vectors_sha3_384	32.200m	501.069ms	49	50	98.00
		kmac_test_vectors_sha3_512	25.337m	416.761ms	47	50	94.00
		kmac_test_vectors_shake_128	1.893h	1.299s	50	50	100.00
		kmac_test_vectors_shake_256	1.609h	221.739ms	45	50	90.00
		kmac_test_vectors_kmac	7.820s	2.092ms	49	50	98.00
		kmac_test_vectors_kmac_xof	7.850s	634.751us	50	50	100.00
V2	sideload	kmac_sideload	8.684m	7.353ms	50	50	100.00
V2	app	kmac_app	7.555m	26.151ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.474m	46.907ms	9	10	90.00
V2	entropy_refresh	kmac_entropy_refresh	7.709m	15.326ms	49	50	98.00
V2	error	kmac_error	8.977m	5.688ms	50	50	100.00
V2	key_error	kmac_key_error	7.890s	6.529ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	1.003m	6.032ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	37.760s	3.997ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.157m	67.657ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	54.660s	844.805us	50	50	100.00
V2	stress_all	kmac_stress_all	1.111h	611.206ms	44	50	88.00
V2	intr_test	kmac_intr_test	0.900s	26.494us	50	50	100.00
V2	alert_test	kmac_alert_test	0.970s	64.698us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.800s	209.375us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.800s	209.375us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.170s	94.285us	5	5	100.00
		kmac_csr_rw	1.380s	457.936us	20	20	100.00
		kmac_csr_aliasing	10.190s	524.311us	5	5	100.00
		kmac_same_csr_outstanding	2.920s	1.449ms	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.170s	94.285us	5	5	100.00
		kmac_csr_rw	1.380s	457.936us	20	20	100.00
		kmac_csr_aliasing	10.190s	524.311us	5	5	100.00
		kmac_same_csr_outstanding	2.920s	1.449ms	20	20	100.00
V2		TOTAL			1026	1050	97.71
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.570s	207.862us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.570s	207.862us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.570s	207.862us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.570s	207.862us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.090s	143.276us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.472m	23.052ms	5	5	100.00
		kmac_tl_intg_err	5.330s	491.851us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.330s	491.851us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	54.660s	844.805us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.634m	28.076ms	49	50	98.00
V2S	sec_cm_key_sideload	kmac_sideload	8.684m	7.353ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.570s	207.862us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.472m	23.052ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.472m	23.052ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.472m	23.052ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.634m	28.076ms	49	50	98.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	54.660s	844.805us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.472m	23.052ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.565m	117.297ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.634m	28.076ms	49	50	98.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	45.651m	97.976ms	17	50	34.00
V3		TOTAL			17	50	34.00
		TOTAL			1232	1290	95.50

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	25	25	14	56.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.06	98.10	92.66	99.89	96.36	95.91	98.89	97.61

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:827) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:
- Test kmac_stress_all_with_rand_reset has 23 failures.
  - 0.kmac_stress_all_with_rand_reset.71144147304597780039066948940610403856277589394774191082138712612513542197980
    Line 756, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 73266794880 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 73266794880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.kmac_stress_all_with_rand_reset.44339580882488035599295618874431085554792208138577480525332945586896116153377
    Line 835, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 21132678806 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 21132678806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 21 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 19 failures:

Test kmac_stress_all has 5 failures.

2.kmac_stress_all.57168442887707420497202037505250282361626215009269541771485663174397639170424
Line 255, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all/latest/run.log

  UVM_ERROR @  34448987 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  34448987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

11.kmac_stress_all.85794926362047775494171885073900940057967845431870734002912757844422339898304
Line 630, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_stress_all/latest/run.log

  UVM_ERROR @ 27095053696 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 27095053696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test kmac_test_vectors_shake_256 has 5 failures.

3.kmac_test_vectors_shake_256.87686142163801296477983916510640181249282797235280660693742572773349150478817
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_test_vectors_shake_256/latest/run.log

  UVM_ERROR @  25057558 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  25057558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

20.kmac_test_vectors_shake_256.75757155188223263375611070975663885141025776278294796163605186543589199962963
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/20.kmac_test_vectors_shake_256/latest/run.log

  UVM_ERROR @  38641117 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  38641117 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test kmac_test_vectors_kmac has 1 failures.

8.kmac_test_vectors_kmac.64987177532033625022311883650752118526364748208949153805128647272478301823778
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_test_vectors_kmac/latest/run.log

  UVM_ERROR @  26859911 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  26859911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_test_vectors_sha3_224 has 1 failures.

10.kmac_test_vectors_sha3_224.106984134112677521644153978942892254728542290484907394494683131769190770848187
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/10.kmac_test_vectors_sha3_224/latest/run.log

  UVM_ERROR @  83181797 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  83181797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_smoke has 1 failures.

13.kmac_smoke.24708852148903211506572800002106690313160335210975427426600802786465163447500
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/13.kmac_smoke/latest/run.log

  UVM_ERROR @ 105112117 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 105112117 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more tests.

UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 9 failures:
- Test kmac_stress_all_with_rand_reset has 9 failures.
  - 11.kmac_stress_all_with_rand_reset.3388345637213195715092407148550653775489998913550458324522873831023328267945
    Line 1063, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 181369929491 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483664 [0x80000010]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 181369929491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 13.kmac_stress_all_with_rand_reset.23023301845392584899549220160362207702861889478036856316948033718833179170209
    Line 1364, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/13.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 88347406589 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483648 [0x80000000]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 88347406589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 3 failures:

Test kmac_app_with_partial_data has 1 failures.

1.kmac_app_with_partial_data.3560609281672377628313327947297618712099223444168080554510129812005986892338
Line 345, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_app_with_partial_data/latest/run.log

  UVM_FATAL @ 6225417976 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (169 [0xa9] vs 19 [0x13]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 6225417976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 1 failures.

13.kmac_stress_all.64841487976040716215837778620783980024954863240475647877555815655619583045647
Line 993, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/13.kmac_stress_all/latest/run.log

  UVM_FATAL @ 59037120361 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (7 [0x7] vs 180 [0xb4]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 59037120361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 1 failures.

26.kmac_entropy_refresh.51761955876779778002958275752426555712408716088671548142379290851695019972960
Line 657, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/26.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 9237540678 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (97 [0x61] vs 212 [0xd4]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 9237540678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test kmac_burst_write has 2 failures.
  - 16.kmac_burst_write.10312334171751653915336390891593030910299090090803317275383178583820731347183
    Line 734, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/16.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 33.kmac_burst_write.14871171478208539925742159839265833652619156779227407696921169565662962890754
    Line 626, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/33.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job kmac_masked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test kmac_long_msg_and_output has 1 failures.
  - 6.kmac_long_msg_and_output.13161066059089580714708169776251273477723502318725784056378799786327145775366
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:f724f1c0-9804-4f9d-b992-2529f6a2f6c0
```
UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 1 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 28.kmac_stress_all_with_rand_reset.5856637106362378786910452410496934462902905524902232427845394129219822296157
    Line 864, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/28.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 87378218914 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 87378218914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```