KMAC/MASKED Simulation Results

Sunday May 05 2024 19:05:13 UTC

GitHub Revision: `d0c52cdadd`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 81579111587980121648949789282063322266496016209500883225240730864920651071561

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.724m	32.525ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.170s	38.737us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.210s	31.258us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	20.240s	18.010ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.000s	392.824us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.700s	289.211us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.210s	31.258us	20	20	100.00
		kmac_csr_aliasing	9.000s	392.824us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.800s	39.950us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.560s	64.693us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	58.807m	329.774ms	46	50	92.00
V2	burst_write	kmac_burst_write	28.566m	65.162ms	48	50	96.00
V2	test_vectors	kmac_test_vectors_sha3_224	52.277m	1.950s	50	50	100.00
		kmac_test_vectors_sha3_256	41.093m	776.431ms	50	50	100.00
		kmac_test_vectors_sha3_384	33.508m	449.207ms	49	50	98.00
		kmac_test_vectors_sha3_512	25.492m	236.830ms	50	50	100.00
		kmac_test_vectors_shake_128	1.795h	739.966ms	50	50	100.00
		kmac_test_vectors_shake_256	1.801h	4.351s	50	50	100.00
		kmac_test_vectors_kmac	7.500s	534.925us	50	50	100.00
		kmac_test_vectors_kmac_xof	7.360s	1.569ms	49	50	98.00
V2	sideload	kmac_sideload	8.845m	69.355ms	50	50	100.00
V2	app	kmac_app	6.386m	11.992ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.149m	138.839ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	7.555m	73.853ms	49	50	98.00
V2	error	kmac_error	8.978m	194.244ms	49	50	98.00
V2	key_error	kmac_key_error	15.330s	8.191ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	50.030s	2.120ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	50.490s	2.133ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.192m	25.930ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	29.360s	1.868ms	50	50	100.00
V2	stress_all	kmac_stress_all	44.216m	33.999ms	47	50	94.00
V2	intr_test	kmac_intr_test	0.890s	70.488us	50	50	100.00
V2	alert_test	kmac_alert_test	0.980s	22.423us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.690s	223.544us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.690s	223.544us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.170s	38.737us	5	5	100.00
		kmac_csr_rw	1.210s	31.258us	20	20	100.00
		kmac_csr_aliasing	9.000s	392.824us	5	5	100.00
		kmac_same_csr_outstanding	2.760s	352.951us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.170s	38.737us	5	5	100.00
		kmac_csr_rw	1.210s	31.258us	20	20	100.00
		kmac_csr_aliasing	9.000s	392.824us	5	5	100.00
		kmac_same_csr_outstanding	2.760s	352.951us	20	20	100.00
V2		TOTAL			1037	1050	98.76
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.480s	97.999us	17	20	85.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.480s	97.999us	17	20	85.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.480s	97.999us	17	20	85.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.480s	97.999us	17	20	85.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.240s	130.481us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.645m	27.774ms	5	5	100.00
		kmac_tl_intg_err	5.490s	886.456us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.490s	886.456us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	29.360s	1.868ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.724m	32.525ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	8.845m	69.355ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.480s	97.999us	17	20	85.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.645m	27.774ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.645m	27.774ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.645m	27.774ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.724m	32.525ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	29.360s	1.868ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.645m	27.774ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.603m	7.885ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.724m	32.525ms	50	50	100.00
V2S		TOTAL			72	75	96.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.194h	103.912ms	12	50	24.00
V3		TOTAL			12	50	24.00
		TOTAL			1236	1290	95.81

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	18	72.00
V2S	5	5	4	80.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.35	97.91	92.64	99.89	77.46	95.59	99.04	97.88

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 33 failures:
- Test kmac_stress_all_with_rand_reset has 33 failures.
  - 0.kmac_stress_all_with_rand_reset.109192615710902883382154817815259712526054010844298814518976775257859692198631
    Line 393, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 33849624069 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 33849624069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.kmac_stress_all_with_rand_reset.26205162861748046559329742442297313830545570115930585368223713349166313224837
    Line 479, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 45414338623 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 45414338623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 31 more failures.
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 5 failures:
- Test kmac_stress_all_with_rand_reset has 5 failures.
  - 1.kmac_stress_all_with_rand_reset.111300518965244123926978938669734014041066599417100398612438332785188581229362
    Line 1923, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 79069693019 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483656 [0x80000008]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 79069693019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 11.kmac_stress_all_with_rand_reset.28562389833155129694251602552955321841669382005877412790136601483519181025405
    Line 1255, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 96106928345 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483672 [0x80000018]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 96106928345 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
Job kmac_masked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 4 failures:
- Test kmac_long_msg_and_output has 4 failures.
  - 12.kmac_long_msg_and_output.94709847520288996067405283236118091057691036550355426215488146905055200558383
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/12.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:e78cb599-9736-4235-ae99-b9ef7253f25b
```
  - 21.kmac_long_msg_and_output.63424299448493675546541392384609295029545446022356823946299832668888006960621
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/21.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:f451df36-af92-4b3c-8183-3addf904c872
```
  - ... and 2 more failures.

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 4 failures:

Test kmac_stress_all has 2 failures.

20.kmac_stress_all.24534835852845066667547426971757138460577819408576391582730755555836784531088
Line 1329, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/20.kmac_stress_all/latest/run.log

  UVM_FATAL @ 125891698911 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (32 [0x20] vs 109 [0x6d]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 125891698911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

35.kmac_stress_all.54552058176227125983104554784077805184895494155549891674383347379897396590916
Line 315, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/35.kmac_stress_all/latest/run.log

  UVM_FATAL @ 4353320006 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (78 [0x4e] vs 115 [0x73]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 4353320006 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_error has 1 failures.

44.kmac_error.84325158220315331646279816809550332669292716355342607788157254535239849831065
Line 257, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/44.kmac_error/latest/run.log

  UVM_FATAL @ 874479919 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (34 [0x22] vs 84 [0x54]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 874479919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 1 failures.

45.kmac_entropy_refresh.84664310426107377517574791414064813718467526653735094676524068113752581583781
Line 801, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/45.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 25333835827 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (41 [0x29] vs 238 [0xee]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 25333835827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: * Check_csr_read_clear_staged_val task: check update_err status has 3 failures:

Test kmac_shadow_reg_errors has 3 failures.

11.kmac_shadow_reg_errors.94968869797900443788588394182077911231447831943715277571093784697648846115697
Line 255, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @  43650383 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  43650383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

13.kmac_shadow_reg_errors.26486101793298285603291108643977504109168116308694518324964515732320533432676
Line 255, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/13.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @  47000439 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  47000439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 3 failures:
- Test kmac_test_vectors_kmac_xof has 1 failures.
  - 16.kmac_test_vectors_kmac_xof.55706348411107983321783897144315192851654520600465867682487761243076055151250
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/16.kmac_test_vectors_kmac_xof/latest/run.log
```
  UVM_ERROR @  87042015 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  87042015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_stress_all has 1 failures.
  - 36.kmac_stress_all.50653495365389207615390692850203427628851016438466586072950805325174915101165
    Line 703, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/36.kmac_stress_all/latest/run.log
```
  UVM_ERROR @ 18129491019 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 18129491019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_sha3_384 has 1 failures.
  - 42.kmac_test_vectors_sha3_384.74791179733334711341970356205083012305188566276322003757661482431933133361438
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/42.kmac_test_vectors_sha3_384/latest/run.log
```
  UVM_ERROR @ 399563236 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 399563236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test kmac_burst_write has 2 failures.
  - 19.kmac_burst_write.28472672853186377297488597789966045626682626769371682005519736311775210089038
    Line 1226, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 33.kmac_burst_write.52476064540715532317226418425737049426102960022787484909806587960652973679524
    Line 746, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/33.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```