KMAC/MASKED Simulation Results

Tuesday May 07 2024 19:02:25 UTC

GitHub Revision: `18c8953cf1`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 23463731882259624708557902606691160899163550314542713462365308032920382521803

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.731m	10.400ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.130s	97.892us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.280s	77.323us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	18.250s	4.020ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.610s	2.009ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.720s	91.199us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.280s	77.323us	20	20	100.00
		kmac_csr_aliasing	9.610s	2.009ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.830s	12.248us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.480s	48.172us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	56.154m	136.841ms	49	50	98.00
V2	burst_write	kmac_burst_write	24.777m	156.825ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	42.321m	606.005ms	49	50	98.00
		kmac_test_vectors_sha3_256	41.559m	370.249ms	50	50	100.00
		kmac_test_vectors_sha3_384	31.177m	70.742ms	50	50	100.00
		kmac_test_vectors_sha3_512	24.625m	535.810ms	49	50	98.00
		kmac_test_vectors_shake_128	1.830h	2.159s	49	50	98.00
		kmac_test_vectors_shake_256	1.611h	3.155s	50	50	100.00
		kmac_test_vectors_kmac	7.240s	3.758ms	49	50	98.00
		kmac_test_vectors_kmac_xof	6.980s	320.580us	50	50	100.00
V2	sideload	kmac_sideload	8.752m	15.731ms	50	50	100.00
V2	app	kmac_app	6.282m	195.626ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.576m	30.704ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	6.800m	66.720ms	49	50	98.00
V2	error	kmac_error	7.832m	8.697ms	46	50	92.00
V2	key_error	kmac_key_error	20.020s	25.670ms	49	50	98.00
V2	edn_timeout_error	kmac_edn_timeout_error	47.360s	12.045ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	48.650s	621.197us	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.169m	7.547ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	23.640s	803.595us	50	50	100.00
V2	stress_all	kmac_stress_all	39.860m	596.287ms	46	50	92.00
V2	intr_test	kmac_intr_test	0.880s	18.183us	50	50	100.00
V2	alert_test	kmac_alert_test	0.910s	23.557us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.440s	475.688us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.440s	475.688us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.130s	97.892us	5	5	100.00
		kmac_csr_rw	1.280s	77.323us	20	20	100.00
		kmac_csr_aliasing	9.610s	2.009ms	5	5	100.00
		kmac_same_csr_outstanding	2.940s	1.685ms	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.130s	97.892us	5	5	100.00
		kmac_csr_rw	1.280s	77.323us	20	20	100.00
		kmac_csr_aliasing	9.610s	2.009ms	5	5	100.00
		kmac_same_csr_outstanding	2.940s	1.685ms	20	20	100.00
V2		TOTAL			1035	1050	98.57
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.450s	57.336us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.450s	57.336us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.450s	57.336us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.450s	57.336us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.830s	124.527us	16	20	80.00
V2S	tl_intg_err	kmac_sec_cm	2.050m	62.234ms	5	5	100.00
		kmac_tl_intg_err	4.970s	1.275ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.970s	1.275ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	23.640s	803.595us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.731m	10.400ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	8.752m	15.731ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.450s	57.336us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	2.050m	62.234ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	2.050m	62.234ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	2.050m	62.234ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.731m	10.400ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	23.640s	803.595us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	2.050m	62.234ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.638m	31.059ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.731m	10.400ms	50	50	100.00
V2S		TOTAL			71	75	94.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	56.201m	108.232ms	19	50	38.00
V3		TOTAL			19	50	38.00
		TOTAL			1240	1290	96.12

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	16	64.00
V2S	5	5	4	80.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.45	97.91	92.68	99.89	78.17	95.59	99.04	97.88

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:
- Test kmac_stress_all_with_rand_reset has 20 failures.
  - 0.kmac_stress_all_with_rand_reset.9111531494684642171035757880042817936091082377056201486227105390416561074017
    Line 454, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10808092726 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 10808092726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.kmac_stress_all_with_rand_reset.81482083340185264134358212910478308459213975436730161230129173880046095325674
    Line 278, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7135438478 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 7135438478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 18 more failures.
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 9 failures:
- Test kmac_stress_all_with_rand_reset has 9 failures.
  - 1.kmac_stress_all_with_rand_reset.65258453151169142446131680068314052702322073155370391370208522856682313660806
    Line 312, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6543993612 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483688 [0x80000028]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 6543993612 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.kmac_stress_all_with_rand_reset.848229263181666647136798441967180219601450770901384532143913893803600960329
    Line 456, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4518956647 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483768 [0x80000078]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 4518956647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.
UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 6 failures:
- Test kmac_error has 3 failures.
  - 0.kmac_error.81828560050201822588573582627617910467694621751308127284169677496373489357793
    Line 391, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_error/latest/run.log
```
  UVM_FATAL @ 10306267420 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 10306267420 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 10.kmac_error.79410753477456152754648592301062666330825421135249307459596202766324542582246
    Line 596, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/10.kmac_error/latest/run.log
```
  UVM_FATAL @ 10021750442 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 10021750442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test kmac_stress_all has 1 failures.
  - 24.kmac_stress_all.9570998334072461719021775028161976328500102705883296542388923291410653221843
    Line 1102, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/24.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 336630609708 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 336630609708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_stress_all_with_rand_reset has 2 failures.
  - 25.kmac_stress_all_with_rand_reset.100221762397573545317598879895312207113361259542550239232106276869085133998973
    Line 3960, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/25.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 288881026538 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 288881026538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 33.kmac_stress_all_with_rand_reset.64792474419756957473079851937338475164964381194341545580977765230649411800709
    Line 2919, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/33.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 941809331990 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 941809331990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 6 failures:
- Test kmac_test_vectors_sha3_512 has 1 failures.
  - 2.kmac_test_vectors_sha3_512.96927308058857002452744317451534112139056733551633763119307781884342734167827
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_test_vectors_sha3_512/latest/run.log
```
  UVM_ERROR @ 102048728 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 102048728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_kmac has 1 failures.
  - 2.kmac_test_vectors_kmac.44658144125660897884322733848955941940747611661194555327085928679226388045251
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_test_vectors_kmac/latest/run.log
```
  UVM_ERROR @  70014531 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  70014531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_sha3_224 has 1 failures.
  - 3.kmac_test_vectors_sha3_224.54432361591464013317061224803384821120722229359783217288446600546324980177938
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_224/latest/run.log
```
  UVM_ERROR @  28332067 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  28332067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_long_msg_and_output has 1 failures.
  - 15.kmac_long_msg_and_output.1204584626807632051735624495757881426446838153722841965023635792366034621064
    Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/15.kmac_long_msg_and_output/latest/run.log
```
  UVM_ERROR @  53422205 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  53422205 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_stress_all has 1 failures.
  - 21.kmac_stress_all.62580146071096156929675681926986061649308106926267181996120236421299353981093
    Line 1402, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/21.kmac_stress_all/latest/run.log
```
  UVM_ERROR @ 61228424869 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 61228424869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 1 more tests.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: * Check_csr_read_clear_staged_val task: check update_err status has 4 failures:
- Test kmac_shadow_reg_errors_with_csr_rw has 4 failures.
  - 0.kmac_shadow_reg_errors_with_csr_rw.42589763785647527607987141817711531100055243924453444792485121884841816627986
    Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @ 248459161 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @ 248459161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.kmac_shadow_reg_errors_with_csr_rw.23551007230304699374493081711834413432965975024257527945380966817286691843634
    Line 255, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @ 195765210 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @ 195765210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 3 failures:

Test kmac_stress_all has 2 failures.

4.kmac_stress_all.9244622135028803384998782133349763723882100029310074056083590123098418878284
Line 2465, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_stress_all/latest/run.log

  UVM_FATAL @ 34913520818 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (243 [0xf3] vs 104 [0x68]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 34913520818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

42.kmac_stress_all.40410318463640147038681670682129671051630859006452481399613160444180065264743
Line 691, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/42.kmac_stress_all/latest/run.log

  UVM_FATAL @ 243979102311 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (229 [0xe5] vs 180 [0xb4]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 243979102311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 1 failures.

44.kmac_entropy_refresh.19459848623715280424660520236108519489828303630449554196792716839402740344917
Line 715, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/44.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 3232255899 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (139 [0x8b] vs 109 [0x6d]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 3232255899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (kmac_base_vseq.sv:382) [kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == *) intr_pins[KmacErr] is not set! has 1 failures:
- Test kmac_key_error has 1 failures.
  - 0.kmac_key_error.75657720632829895262317822999757799821247855093058917850302865308290418334753
    Line 259, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_key_error/latest/run.log
```
  UVM_ERROR @ 439529059 ps: (kmac_base_vseq.sv:382) [uvm_test_top.env.virtual_sequencer.kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == 1) intr_pins[KmacErr] is not set!
  UVM_INFO @ 439529059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_error has 1 failures.
  - 23.kmac_error.79325029671792570040973119810571632575448317642125303992369011944619995143804
    Line 772, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/23.kmac_error/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```