KMAC/MASKED Simulation Results

Thursday May 09 2024 19:02:32 UTC

GitHub Revision: `9656691e03`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 30170103562476460183108208532025718695603957360441815475011549460912256789439

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.649m	5.135ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.180s	310.775us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.230s	61.543us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	21.050s	975.936us	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.160s	1.021ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.590s	116.389us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.230s	61.543us	20	20	100.00
		kmac_csr_aliasing	10.160s	1.021ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.780s	13.644us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.540s	156.882us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	56.425m	201.212ms	50	50	100.00
V2	burst_write	kmac_burst_write	30.735m	58.925ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	44.762m	401.705ms	50	50	100.00
		kmac_test_vectors_sha3_256	42.101m	438.362ms	50	50	100.00
		kmac_test_vectors_sha3_384	32.652m	603.141ms	50	50	100.00
		kmac_test_vectors_sha3_512	23.873m	1.031s	50	50	100.00
		kmac_test_vectors_shake_128	1.889h	1.041s	49	50	98.00
		kmac_test_vectors_shake_256	1.724h	1.851s	50	50	100.00
		kmac_test_vectors_kmac	6.860s	268.984us	50	50	100.00
		kmac_test_vectors_kmac_xof	7.350s	1.149ms	48	50	96.00
V2	sideload	kmac_sideload	8.499m	18.445ms	50	50	100.00
V2	app	kmac_app	7.502m	23.302ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.819m	52.645ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	7.662m	73.989ms	50	50	100.00
V2	error	kmac_error	8.065m	42.403ms	48	50	96.00
V2	key_error	kmac_key_error	12.820s	7.000ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	35.000s	2.633ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	46.860s	6.145ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.259m	30.970ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	30.350s	3.979ms	50	50	100.00
V2	stress_all	kmac_stress_all	49.552m	159.601ms	46	50	92.00
V2	intr_test	kmac_intr_test	0.920s	30.400us	50	50	100.00
V2	alert_test	kmac_alert_test	0.910s	63.871us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.640s	474.218us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.640s	474.218us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.180s	310.775us	5	5	100.00
		kmac_csr_rw	1.230s	61.543us	20	20	100.00
		kmac_csr_aliasing	10.160s	1.021ms	5	5	100.00
		kmac_same_csr_outstanding	2.740s	1.058ms	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.180s	310.775us	5	5	100.00
		kmac_csr_rw	1.230s	61.543us	20	20	100.00
		kmac_csr_aliasing	10.160s	1.021ms	5	5	100.00
		kmac_same_csr_outstanding	2.740s	1.058ms	20	20	100.00
V2		TOTAL			1040	1050	99.05
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.420s	127.180us	15	20	75.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.420s	127.180us	15	20	75.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.420s	127.180us	15	20	75.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.420s	127.180us	15	20	75.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.780s	1.430ms	18	20	90.00
V2S	tl_intg_err	kmac_sec_cm	1.476m	20.666ms	5	5	100.00
		kmac_tl_intg_err	6.190s	3.022ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	6.190s	3.022ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	30.350s	3.979ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.649m	5.135ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	8.499m	18.445ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.420s	127.180us	15	20	75.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.476m	20.666ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.476m	20.666ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.476m	20.666ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.649m	5.135ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	30.350s	3.979ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.476m	20.666ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.613m	24.447ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.649m	5.135ms	50	50	100.00
V2S		TOTAL			68	75	90.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	54.178m	140.213ms	18	50	36.00
V3		TOTAL			18	50	36.00
		TOTAL			1241	1290	96.20

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	20	80.00
V2S	5	5	3	60.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.24	97.91	92.64	99.89	76.76	95.59	99.04	97.88

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 29 failures:
- Test kmac_stress_all_with_rand_reset has 29 failures.
  - 1.kmac_stress_all_with_rand_reset.38969614152350914167083575294334598421169520920639588949438357081528787158920
    Line 391, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 11909028893 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 11909028893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.kmac_stress_all_with_rand_reset.61552068430928447671566226906145233098759456414991947888844167622782274708196
    Line 581, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6659979629 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 6659979629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 27 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: * Check_csr_read_clear_staged_val task: check update_err status has 7 failures:

Test kmac_shadow_reg_errors_with_csr_rw has 2 failures.

4.kmac_shadow_reg_errors_with_csr_rw.101272305662365232270925290326185715199725098493981469393996319405858414092639
Line 255, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  60149122 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  60149122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

17.kmac_shadow_reg_errors_with_csr_rw.91976056486322677868858345470249019606234722502650177236636448683441347656368
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/17.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  19581367 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  19581367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_shadow_reg_errors has 5 failures.

8.kmac_shadow_reg_errors.5897152444059322198416162567181236371741174538778850558679712297318044558245
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @   4841263 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @   4841263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.kmac_shadow_reg_errors.13539723957614137927804983383886890286829378272069033630270792616064474095621
Line 255, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @  20238836 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  20238836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
- Test kmac_test_vectors_shake_128 has 1 failures.
  - 2.kmac_test_vectors_shake_128.60295271285747798553193162919629589485180135927095374021599918924380049998428
    Line 4481, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_test_vectors_shake_128/latest/run.log
```
  UVM_FATAL @ 5000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 5000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 5000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_error has 1 failures.
  - 25.kmac_error.85305019587047757564827146720169321591740748065743194039804059335286394649792
    Line 870, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/25.kmac_error/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_burst_write has 1 failures.
  - 30.kmac_burst_write.713034864739830118321515478970792417915063072652382392282835150782648612367
    Line 926, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/30.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 3 failures:
- Test kmac_stress_all has 2 failures.
  - 5.kmac_stress_all.100459140651574241763181615768401869614367166793294506293030586818694493508359
    Line 2875, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 179428236673 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 179428236673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 41.kmac_stress_all.59834881322906506748535372142211407031210810036813385196925277666663576007753
    Line 710, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/41.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 33730854402 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 33730854402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_error has 1 failures.
  - 24.kmac_error.50330932105131696313581174227273631216174247893496298053504524941330795901073
    Line 401, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/24.kmac_error/latest/run.log
```
  UVM_FATAL @ 10314647020 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 10314647020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 3 failures:
- Test kmac_stress_all_with_rand_reset has 3 failures.
  - 6.kmac_stress_all_with_rand_reset.22540809980345121663549745159549182566009945295857572236558985864105975140467
    Line 263, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  42536927 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483736 [0x80000058]) reg name: kmac_reg_block.err_code
  UVM_INFO @  42536927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 22.kmac_stress_all_with_rand_reset.14972507440740220026906676680543454279732647192919269510599614365477885416248
    Line 427, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/22.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5575007609 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483656 [0x80000008]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 5575007609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 3 failures:
- Test kmac_test_vectors_kmac_xof has 2 failures.
  - 35.kmac_test_vectors_kmac_xof.87598689512554406920550708739344346462099547084072679088310368851508984042448
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/35.kmac_test_vectors_kmac_xof/latest/run.log
```
  UVM_ERROR @  38322269 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  38322269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 42.kmac_test_vectors_kmac_xof.18490235198490820987832319360374451047149929184860850850803985306921455399591
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/42.kmac_test_vectors_kmac_xof/latest/run.log
```
  UVM_ERROR @  44114229 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  44114229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_stress_all has 1 failures.
  - 48.kmac_stress_all.25524126522147121025880910757666350805706124953582756930962135028433184167930
    Line 1063, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/48.kmac_stress_all/latest/run.log
```
  UVM_ERROR @ 21888872212 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 21888872212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 1 failures:
- Test kmac_stress_all has 1 failures.
  - 19.kmac_stress_all.93972444432786255738786003482367148291442269464785335210998447355014180869998
    Line 287, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 290212763 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (181 [0xb5] vs 171 [0xab]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 290212763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```