KMAC/MASKED Simulation Results

Monday June 24 2024 23:02:35 UTC

GitHub Revision: `6e698b4dfe`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 102849012855470111388983783327793201144267754054590670930996118558901483180117

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.585m	19.788ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.210s	129.190us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.240s	125.997us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	21.630s	5.679ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	8.470s	561.322us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.860s	281.568us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.240s	125.997us	20	20	100.00
		kmac_csr_aliasing	8.470s	561.322us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.820s	36.087us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.460s	33.347us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	56.774m	364.707ms	50	50	100.00
V2	burst_write	kmac_burst_write	25.675m	27.702ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	45.413m	1.648s	50	50	100.00
		kmac_test_vectors_sha3_256	41.056m	537.652ms	50	50	100.00
		kmac_test_vectors_sha3_384	32.218m	304.024ms	49	50	98.00
		kmac_test_vectors_sha3_512	24.159m	98.893ms	50	50	100.00
		kmac_test_vectors_shake_128	1.838h	1.298s	50	50	100.00
		kmac_test_vectors_shake_256	1.553h	448.442ms	50	50	100.00
		kmac_test_vectors_kmac	7.500s	3.032ms	50	50	100.00
		kmac_test_vectors_kmac_xof	7.310s	759.758us	50	50	100.00
V2	sideload	kmac_sideload	9.215m	19.667ms	50	50	100.00
V2	app	kmac_app	7.560m	18.403ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.782m	7.579ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	6.679m	15.780ms	49	50	98.00
V2	error	kmac_error	8.835m	12.125ms	50	50	100.00
V2	key_error	kmac_key_error	18.420s	15.476ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	42.540s	2.213ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	39.280s	1.651ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	33.240s	9.298ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	42.050s	3.180ms	50	50	100.00
V2	stress_all	kmac_stress_all	48.559m	30.151ms	47	50	94.00
V2	intr_test	kmac_intr_test	0.900s	148.225us	50	50	100.00
V2	alert_test	kmac_alert_test	0.970s	201.241us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.630s	156.186us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.630s	156.186us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.210s	129.190us	5	5	100.00
		kmac_csr_rw	1.240s	125.997us	20	20	100.00
		kmac_csr_aliasing	8.470s	561.322us	5	5	100.00
		kmac_same_csr_outstanding	2.750s	453.170us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.210s	129.190us	5	5	100.00
		kmac_csr_rw	1.240s	125.997us	20	20	100.00
		kmac_csr_aliasing	8.470s	561.322us	5	5	100.00
		kmac_same_csr_outstanding	2.750s	453.170us	20	20	100.00
V2		TOTAL			1044	1050	99.43
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.630s	348.783us	17	20	85.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.630s	348.783us	17	20	85.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.630s	348.783us	17	20	85.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.630s	348.783us	17	20	85.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.050s	146.478us	16	20	80.00
V2S	tl_intg_err	kmac_sec_cm	1.791m	32.181ms	5	5	100.00
		kmac_tl_intg_err	5.260s	909.544us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.260s	909.544us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	42.050s	3.180ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.585m	19.788ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	9.215m	19.667ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.630s	348.783us	17	20	85.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.791m	32.181ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.791m	32.181ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.791m	32.181ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.585m	19.788ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	42.050s	3.180ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.791m	32.181ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.889m	13.359ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.585m	19.788ms	50	50	100.00
V2S		TOTAL			68	75	90.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	22.964m	242.246ms	6	10	60.00
V3		TOTAL			6	10	60.00
		TOTAL			1233	1250	98.64

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	21	84.00
V2S	5	5	3	60.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.94	97.91	92.65	99.89	74.65	95.59	99.05	97.88

Failure Buckets

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: * Check_csr_read_clear_staged_val task: check update_err status has 7 failures:

Test kmac_shadow_reg_errors_with_csr_rw has 4 failures.

2.kmac_shadow_reg_errors_with_csr_rw.66708005280624353102938653013128568287513735310209142275091584200074249455678
Line 255, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @ 162389219 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @ 162389219 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.kmac_shadow_reg_errors_with_csr_rw.31514416766988054045263834743128111064182813230064864476902209470423512209756
Line 255, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  43062170 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  43062170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test kmac_shadow_reg_errors has 3 failures.

9.kmac_shadow_reg_errors.37963643690758550628698937920992431577832053026473398410319551304726166013114
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @  42070570 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  42070570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

14.kmac_shadow_reg_errors.43366408729297618518119027353188906092548611151377891260765963671512290431364
Line 255, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @  10099483 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  10099483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (cip_base_vseq.sv:828) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
- Test kmac_stress_all_with_rand_reset has 3 failures.
  - 3.kmac_stress_all_with_rand_reset.92154635771467941768513701459873242529832527377328054458964208717668688140502
    Line 1090, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 196203287239 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 196203287239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.kmac_stress_all_with_rand_reset.6295553817677115910881655842742164646370509037989512695359865243633970482243
    Line 298, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 13283629143 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 13283629143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 3 failures:
- Test kmac_stress_all has 3 failures.
  - 14.kmac_stress_all.78151832355709533759319409908030734252971275802647858585966461341554240803713
    Line 2148, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 154597739661 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 154597739661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 48.kmac_stress_all.40294247189056667565726796968261195390618426726708521746038083888671455204169
    Line 864, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/48.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 97917746940 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 97917746940 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 0.kmac_stress_all_with_rand_reset.60960628830819342323651613686093766589640224830782136078196701204377013626202
    Line 1216, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 54177226652 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483688 [0x80000028]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 54177226652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 1 failures:
- Test kmac_test_vectors_sha3_384 has 1 failures.
  - 4.kmac_test_vectors_sha3_384.48546206241924196811014438450169607299128457414682050376676231799584730121206
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_384/latest/run.log
```
  UVM_ERROR @  31688323 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  31688323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_burst_write has 1 failures.
  - 20.kmac_burst_write.91047759766862905793216325129515787831568750601998847192073716641712896499587
    Line 800, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/20.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 1 failures:
- Test kmac_entropy_refresh has 1 failures.
  - 44.kmac_entropy_refresh.58562229932583025417850165643262488256714322670425631870025639390890117409686
    Line 959, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/44.kmac_entropy_refresh/latest/run.log
```
  UVM_FATAL @ 13422643928 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (60 [0x3c] vs 211 [0xd3]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 13422643928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```