KMAC/MASKED Simulation Results

Monday June 10 2024 23:28:43 UTC

GitHub Revision: `a8c9c17a8c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 72227341233107832543509484606850665418885932500709631655793413524197290927900

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.818m	13.230ms	49	50	98.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.110s	47.707us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.200s	150.130us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	19.140s	975.479us	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.190s	730.335us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.830s	1.009ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.200s	150.130us	20	20	100.00
		kmac_csr_aliasing	9.190s	730.335us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.810s	34.476us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.490s	79.652us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	long_msg_and_output	kmac_long_msg_and_output	54.124m	420.293ms	49	50	98.00
V2	burst_write	kmac_burst_write	28.744m	14.968ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	41.756m	442.343ms	50	50	100.00
		kmac_test_vectors_sha3_256	39.346m	94.810ms	49	50	98.00
		kmac_test_vectors_sha3_384	37.287m	1.397s	50	50	100.00
		kmac_test_vectors_sha3_512	24.003m	559.973ms	50	50	100.00
		kmac_test_vectors_shake_128	1.855h	978.449ms	50	50	100.00
		kmac_test_vectors_shake_256	1.484h	2.516s	50	50	100.00
		kmac_test_vectors_kmac	7.260s	1.024ms	50	50	100.00
		kmac_test_vectors_kmac_xof	7.350s	3.018ms	50	50	100.00
V2	sideload	kmac_sideload	9.107m	6.155ms	50	50	100.00
V2	app	kmac_app	6.950m	52.593ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.684m	18.280ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	7.535m	41.833ms	48	50	96.00
V2	error	kmac_error	9.453m	84.574ms	49	50	98.00
V2	key_error	kmac_key_error	13.370s	1.876ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	1.036m	6.907ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	46.400s	7.234ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.347m	31.321ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	58.960s	8.938ms	50	50	100.00
V2	stress_all	kmac_stress_all	1.133h	43.928ms	44	50	88.00
V2	intr_test	kmac_intr_test	0.890s	27.187us	50	50	100.00
V2	alert_test	kmac_alert_test	0.910s	60.387us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.240s	484.611us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.240s	484.611us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.110s	47.707us	5	5	100.00
		kmac_csr_rw	1.200s	150.130us	20	20	100.00
		kmac_csr_aliasing	9.190s	730.335us	5	5	100.00
		kmac_same_csr_outstanding	2.720s	121.931us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.110s	47.707us	5	5	100.00
		kmac_csr_rw	1.200s	150.130us	20	20	100.00
		kmac_csr_aliasing	9.190s	730.335us	5	5	100.00
		kmac_same_csr_outstanding	2.720s	121.931us	20	20	100.00
V2		TOTAL			1039	1050	98.95
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.370s	92.481us	17	20	85.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.370s	92.481us	17	20	85.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.370s	92.481us	17	20	85.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.370s	92.481us	17	20	85.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.310s	275.209us	17	20	85.00
V2S	tl_intg_err	kmac_sec_cm	2.028m	9.019ms	5	5	100.00
		kmac_tl_intg_err	5.000s	960.651us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.000s	960.651us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	58.960s	8.938ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.818m	13.230ms	49	50	98.00
V2S	sec_cm_key_sideload	kmac_sideload	9.107m	6.155ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.370s	92.481us	17	20	85.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	2.028m	9.019ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	2.028m	9.019ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	2.028m	9.019ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.818m	13.230ms	49	50	98.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	58.960s	8.938ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	2.028m	9.019ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	7.789m	70.787ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.818m	13.230ms	49	50	98.00
V2S		TOTAL			69	75	92.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	48.210m	379.738ms	20	50	40.00
V3		TOTAL			20	50	40.00
		TOTAL			1242	1290	96.28

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	25	25	20	80.00
V2S	5	5	3	60.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.20	97.89	92.58	99.89	76.76	95.53	98.89	97.88

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 21 failures:
- Test kmac_stress_all_with_rand_reset has 21 failures.
  - 1.kmac_stress_all_with_rand_reset.64085752656363103728575729491755521827942341291099250651086712860264169332203
    Line 606, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 28671820887 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 28671820887 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.kmac_stress_all_with_rand_reset.75886367803934086432642214397675454852880594450233225776861059340772578953836
    Line 258, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 222273958 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 222273958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 19 more failures.
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 8 failures:
- Test kmac_stress_all_with_rand_reset has 8 failures.
  - 9.kmac_stress_all_with_rand_reset.32394138791258794149210695285345068278186037939769013582127608637120217413564
    Line 374, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3495539437 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483712 [0x80000040]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 3495539437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 18.kmac_stress_all_with_rand_reset.42187592954707037407723656243862009133012000748148213039558725874329510183428
    Line 511, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/18.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3307897586 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483728 [0x80000050]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 3307897586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: * Check_csr_read_clear_staged_val task: check update_err status has 6 failures:

Test kmac_shadow_reg_errors has 3 failures.

0.kmac_shadow_reg_errors.34041802954012081810790351904761556301579504762366791402080805096038525630953
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @  15843533 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  15843533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.kmac_shadow_reg_errors.50302854182377054130983313493601772809823132750837732928005974158876245798540
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @   4499895 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @   4499895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test kmac_shadow_reg_errors_with_csr_rw has 3 failures.

1.kmac_shadow_reg_errors_with_csr_rw.93570707982082271326884177762944521374320563029744046534953302636312455433134
Line 255, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @ 323706859 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @ 323706859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.kmac_shadow_reg_errors_with_csr_rw.106002715180350933941082442423975617620332781988602732996602373227434263669694
Line 255, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  31742378 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  31742378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 5 failures:

Test kmac_test_vectors_sha3_256 has 1 failures.

9.kmac_test_vectors_sha3_256.94398882105351153301268167270416430007610962085020713901402618874255863001447
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_test_vectors_sha3_256/latest/run.log

  UVM_ERROR @ 280994582 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 280994582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_smoke has 1 failures.

14.kmac_smoke.19732886025632095672370025351131850988987015062954483754398147362832082151614
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_smoke/latest/run.log

  UVM_ERROR @  26757734 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  26757734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 2 failures.

23.kmac_stress_all.47076939026450585367644279871011144261164227274206394803212183322189621787162
Line 399, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/23.kmac_stress_all/latest/run.log

  UVM_ERROR @ 2902191357 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 2902191357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

38.kmac_stress_all.79433560641804441442209234871381224069820836378272769841699390161953156457429
Line 283, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/38.kmac_stress_all/latest/run.log

  UVM_ERROR @ 483683101 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 483683101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 1 failures.

44.kmac_entropy_refresh.98168174392850407171582009249952381174393291257724828694741888056382536858028
Line 390, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/44.kmac_entropy_refresh/latest/run.log

  UVM_ERROR @ 3887851737 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 3887851737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 4 failures:
- Test kmac_stress_all has 3 failures.
  - 7.kmac_stress_all.58744199974938808820004915961228942846258886771710837777208045088322946310394
    Line 858, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 26462621604 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 26462621604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 14.kmac_stress_all.61582908604454309326335202738700909251657212597518244339020569079856134671478
    Line 1932, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 115434991089 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 115434991089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 42.kmac_stress_all_with_rand_reset.59352797478244150617863150974915718051193606814331534177204092279614854193439
    Line 955, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/42.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 60957494385 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 60957494385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 2 failures:
- Test kmac_stress_all has 1 failures.
  - 12.kmac_stress_all.13506276966916216897033791089824975183843936928809982244032260379921308903468
    Line 739, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/12.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 10684633967 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (239 [0xef] vs 158 [0x9e]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 10684633967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_entropy_refresh has 1 failures.
  - 15.kmac_entropy_refresh.70911378038062281536084267632789479906509223389968240658857822717101527670708
    Line 397, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/15.kmac_entropy_refresh/latest/run.log
```
  UVM_FATAL @ 2921892664 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (41 [0x29] vs 37 [0x25]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 2921892664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_error has 1 failures.
  - 9.kmac_error.27831753888321614461765777437042151765620512811881752991073841757878562591586
    Line 1153, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_error/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job kmac_masked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test kmac_long_msg_and_output has 1 failures.
  - 28.kmac_long_msg_and_output.106060899441422869844277999694559947775287776764187293605278208572337889645904
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/28.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:cd98c7cd-d622-4de6-b693-01099ccecad6
```