KMAC/MASKED Simulation Results

Thursday June 13 2024 19:02:12 UTC

GitHub Revision: `548a3880d8`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 95435389850697596633112362018639443702533575559488568730544091582583938649085

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.519m	18.038ms	49	50	98.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.220s	32.304us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.220s	31.262us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	19.780s	3.558ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.260s	1.811ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.690s	374.652us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.220s	31.262us	20	20	100.00
		kmac_csr_aliasing	9.260s	1.811ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.780s	25.554us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.520s	44.973us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	long_msg_and_output	kmac_long_msg_and_output	57.318m	427.622ms	48	50	96.00
V2	burst_write	kmac_burst_write	31.421m	16.058ms	48	50	96.00
V2	test_vectors	kmac_test_vectors_sha3_224	43.610m	393.139ms	50	50	100.00
		kmac_test_vectors_sha3_256	39.225m	362.519ms	50	50	100.00
		kmac_test_vectors_sha3_384	31.022m	1.197s	50	50	100.00
		kmac_test_vectors_sha3_512	23.233m	56.831ms	50	50	100.00
		kmac_test_vectors_shake_128	1.861h	2.195s	50	50	100.00
		kmac_test_vectors_shake_256	1.528h	426.146ms	50	50	100.00
		kmac_test_vectors_kmac	6.930s	861.595us	50	50	100.00
		kmac_test_vectors_kmac_xof	7.500s	678.167us	49	50	98.00
V2	sideload	kmac_sideload	9.149m	140.248ms	50	50	100.00
V2	app	kmac_app	6.784m	13.144ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	7.392m	176.007ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	7.268m	86.025ms	49	50	98.00
V2	error	kmac_error	7.423m	5.553ms	49	50	98.00
V2	key_error	kmac_key_error	14.200s	3.868ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	40.640s	3.362ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	43.980s	2.451ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.265m	33.203ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	41.900s	565.879us	50	50	100.00
V2	stress_all	kmac_stress_all	59.681m	127.780ms	49	50	98.00
V2	intr_test	kmac_intr_test	0.900s	16.770us	50	50	100.00
V2	alert_test	kmac_alert_test	0.940s	83.318us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.290s	142.854us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.290s	142.854us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.220s	32.304us	5	5	100.00
		kmac_csr_rw	1.220s	31.262us	20	20	100.00
		kmac_csr_aliasing	9.260s	1.811ms	5	5	100.00
		kmac_same_csr_outstanding	2.560s	356.909us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.220s	32.304us	5	5	100.00
		kmac_csr_rw	1.220s	31.262us	20	20	100.00
		kmac_csr_aliasing	9.260s	1.811ms	5	5	100.00
		kmac_same_csr_outstanding	2.560s	356.909us	20	20	100.00
V2		TOTAL			1042	1050	99.24
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.580s	131.243us	19	20	95.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.580s	131.243us	19	20	95.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.580s	131.243us	19	20	95.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.580s	131.243us	19	20	95.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.100s	564.660us	18	20	90.00
V2S	tl_intg_err	kmac_sec_cm	1.808m	16.208ms	5	5	100.00
		kmac_tl_intg_err	5.110s	209.741us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.110s	209.741us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	41.900s	565.879us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.519m	18.038ms	49	50	98.00
V2S	sec_cm_key_sideload	kmac_sideload	9.149m	140.248ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.580s	131.243us	19	20	95.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.808m	16.208ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.808m	16.208ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.808m	16.208ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.519m	18.038ms	49	50	98.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	41.900s	565.879us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.808m	16.208ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.905m	25.688ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.519m	18.038ms	49	50	98.00
V2S		TOTAL			72	75	96.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	51.513m	55.539ms	15	50	30.00
V3		TOTAL			15	50	30.00
		TOTAL			1243	1290	96.36

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	25	25	19	76.00
V2S	5	5	3	60.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.15	97.91	92.65	99.89	76.06	95.59	99.05	97.88

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 26 failures:
- Test kmac_stress_all_with_rand_reset has 26 failures.
  - 0.kmac_stress_all_with_rand_reset.72623537443164872221820536095007887869805803947272229101552730747217641387274
    Line 436, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 776208432 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 776208432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.113673880219584336570603193832193960706833995243862453078797177342991628674820
    Line 820, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 14271735762 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 14271735762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 24 more failures.
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 7 failures:
- Test kmac_stress_all_with_rand_reset has 7 failures.
  - 5.kmac_stress_all_with_rand_reset.54391809475994473746311864517423118871726912827567391566370580928084191901296
    Line 437, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9170406972 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483744 [0x80000060]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 9170406972 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.kmac_stress_all_with_rand_reset.76508590905636192261910157768686640753616491091872210079634198987618112034024
    Line 262, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  11696265 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483744 [0x80000060]) reg name: kmac_reg_block.err_code
  UVM_INFO @  11696265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: * Check_csr_read_clear_staged_val task: check update_err status has 3 failures:

Test kmac_shadow_reg_errors_with_csr_rw has 2 failures.

7.kmac_shadow_reg_errors_with_csr_rw.111509589537349149526243467304787325672500029734168094155966697992108214180185
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @   8231173 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @   8231173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

12.kmac_shadow_reg_errors_with_csr_rw.7294212219789993126565904906523623468262806739426930320722282927426542165930
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/12.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  26970593 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  26970593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_shadow_reg_errors has 1 failures.

10.kmac_shadow_reg_errors.102674795600850980147437757473305330041363763216944100071543625153328892488159
Line 255, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/10.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @  17250377 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  17250377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 3 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 20.kmac_stress_all_with_rand_reset.65065466231943217040588177231010144506738185589558594195464513260095079178576
    Line 422, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/20.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10375842305 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 10375842305 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_kmac_xof has 1 failures.
  - 23.kmac_test_vectors_kmac_xof.66222164703871544250365032613197850124614212467277200651696915361654664414616
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/23.kmac_test_vectors_kmac_xof/latest/run.log
```
  UVM_ERROR @  70161233 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  70161233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_smoke has 1 failures.
  - 41.kmac_smoke.39335008382292278936894196239362069840045741972804379146690041664223787321954
    Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/41.kmac_smoke/latest/run.log
```
  UVM_ERROR @ 111764270 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 111764270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job kmac_masked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:
- Test kmac_long_msg_and_output has 2 failures.
  - 4.kmac_long_msg_and_output.30160920279920056362654986450567055145661116922590310741679372209920289314410
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:7b517815-5fd2-4465-ad12-2cbef46f2198
```
  - 41.kmac_long_msg_and_output.13592660315853671944942359557880282996495968508899793946548650704428198200339
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/41.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:cfc063f9-1790-4ef3-8609-54816ce2f87d
```
UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 2 failures:
- Test kmac_error has 1 failures.
  - 4.kmac_error.63344085051413214838883041379193889461794939095875772953653219808867992423874
    Line 476, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_error/latest/run.log
```
  UVM_FATAL @ 17102572131 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (156 [0x9c] vs 106 [0x6a]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 17102572131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_entropy_refresh has 1 failures.
  - 27.kmac_entropy_refresh.103119657751104409668546605393409606939733682744728642280343589665096448570880
    Line 547, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/27.kmac_entropy_refresh/latest/run.log
```
  UVM_FATAL @ 39818878904 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (15 [0xf] vs 199 [0xc7]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 39818878904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test kmac_burst_write has 2 failures.
  - 14.kmac_burst_write.1530380283139619826964084366353206910810960583536346810966484690174225365933
    Line 560, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 41.kmac_burst_write.50317999641310578648422544789583059320117991626216093912403924679902163099199
    Line 1070, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/41.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 2 failures:
- Test kmac_stress_all has 1 failures.
  - 16.kmac_stress_all.21159790843510025905920980515349999800952526649888550774655917167019899996699
    Line 782, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/16.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 83406587920 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 83406587920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 39.kmac_stress_all_with_rand_reset.73361542163007771285110883127623946531343124369966390357360444236008856648085
    Line 2000, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/39.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 146703970484 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 146703970484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```