KMAC/MASKED Simulation Results

Friday June 21 2024 23:02:45 UTC

GitHub Revision: `de38ce313c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 40294666978553523170681160506532247841705182588034413483474981853853670477454

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.503m	12.762ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.170s	82.403us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.220s	114.573us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	19.440s	3.862ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.180s	929.299us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.810s	48.109us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.220s	114.573us	20	20	100.00
		kmac_csr_aliasing	10.180s	929.299us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.770s	10.929us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.370s	18.416us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	58.333m	257.884ms	49	50	98.00
V2	burst_write	kmac_burst_write	27.534m	34.342ms	46	50	92.00
V2	test_vectors	kmac_test_vectors_sha3_224	43.572m	411.825ms	49	50	98.00
		kmac_test_vectors_sha3_256	40.167m	391.039ms	50	50	100.00
		kmac_test_vectors_sha3_384	33.122m	443.413ms	50	50	100.00
		kmac_test_vectors_sha3_512	23.865m	411.358ms	50	50	100.00
		kmac_test_vectors_shake_128	1.892h	2.972s	49	50	98.00
		kmac_test_vectors_shake_256	1.654h	1.220s	50	50	100.00
		kmac_test_vectors_kmac	7.200s	284.228us	50	50	100.00
		kmac_test_vectors_kmac_xof	7.080s	265.825us	50	50	100.00
V2	sideload	kmac_sideload	9.391m	96.291ms	50	50	100.00
V2	app	kmac_app	7.254m	127.160ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	7.070m	31.769ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	7.155m	66.747ms	49	50	98.00
V2	error	kmac_error	8.216m	19.185ms	46	50	92.00
V2	key_error	kmac_key_error	17.850s	27.395ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	55.420s	6.524ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	39.800s	1.665ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.389m	32.684ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	47.670s	1.007ms	50	50	100.00
V2	stress_all	kmac_stress_all	55.539m	32.451ms	48	50	96.00
V2	intr_test	kmac_intr_test	0.880s	53.803us	50	50	100.00
V2	alert_test	kmac_alert_test	1.010s	144.929us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.210s	736.746us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.210s	736.746us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.170s	82.403us	5	5	100.00
		kmac_csr_rw	1.220s	114.573us	20	20	100.00
		kmac_csr_aliasing	10.180s	929.299us	5	5	100.00
		kmac_same_csr_outstanding	2.920s	1.027ms	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.170s	82.403us	5	5	100.00
		kmac_csr_rw	1.220s	114.573us	20	20	100.00
		kmac_csr_aliasing	10.180s	929.299us	5	5	100.00
		kmac_same_csr_outstanding	2.920s	1.027ms	20	20	100.00
V2		TOTAL			1035	1050	98.57
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.520s	109.787us	16	20	80.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.520s	109.787us	16	20	80.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.520s	109.787us	16	20	80.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.520s	109.787us	16	20	80.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.010s	994.563us	19	20	95.00
V2S	tl_intg_err	kmac_sec_cm	1.885m	7.930ms	5	5	100.00
		kmac_tl_intg_err	5.240s	4.712ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.240s	4.712ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	47.670s	1.007ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.503m	12.762ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	9.391m	96.291ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.520s	109.787us	16	20	80.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.885m	7.930ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.885m	7.930ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.885m	7.930ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.503m	12.762ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	47.670s	1.007ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.885m	7.930ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.335m	53.574ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.503m	12.762ms	50	50	100.00
V2S		TOTAL			70	75	93.33
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	32.143m	70.044ms	4	10	40.00
V3		TOTAL			4	10	40.00
		TOTAL			1224	1250	97.92

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	17	68.00
V2S	5	5	3	60.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.20	97.89	92.58	99.89	76.76	95.53	98.89	97.88

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 6 failures:
- Test kmac_error has 1 failures.
  - 2.kmac_error.59185515231762455529455401542488986504579344720814122528259476425103737773890
    Line 1005, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_error/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_burst_write has 4 failures.
  - 8.kmac_burst_write.32751163941606597903761081487596124495434568694142782681491339997799368463670
    Line 1220, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 13.kmac_burst_write.27045128859880589408032413294502912373919508296735972163070515554832649692633
    Line 794, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/13.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
- Test kmac_app has 1 failures.
  - 35.kmac_app.79552281697933482623434384119323807753054501418618995437405341020752959290104
    Line 808, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/35.kmac_app/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: * Check_csr_read_clear_staged_val task: check update_err status has 5 failures:

Test kmac_shadow_reg_errors has 4 failures.

2.kmac_shadow_reg_errors.29369923073056067037401649369328703993485989232060212260084348603542738582907
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @  17115254 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  17115254 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.kmac_shadow_reg_errors.66284205777344380564103772704047525116544909523268038816592685331092963663319
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @  23351899 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  23351899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

19.kmac_shadow_reg_errors_with_csr_rw.44454981847578183292011599918296521101301322771623868136854621929686549651766
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  10862493 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  10862493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:828) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 4 failures:
- Test kmac_stress_all_with_rand_reset has 4 failures.
  - 0.kmac_stress_all_with_rand_reset.74077390717538683532682898128132666449018273044758180845590382123414017128840
    Line 1338, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 67493515619 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 67493515619 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.43735247774737874816970079740657240684673101407963046543400058298053449900476
    Line 1060, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 16782567002 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 16782567002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 4 failures:
- Test kmac_error has 3 failures.
  - 6.kmac_error.32448497694158393244731851456519011516752881648016066942084451727234083011960
    Line 542, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_error/latest/run.log
```
  UVM_FATAL @ 10131462802 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 10131462802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.kmac_error.74056113756138651713145528000557110138186922034940962841257780422648755798563
    Line 720, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_error/latest/run.log
```
  UVM_FATAL @ 10086567840 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 10086567840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test kmac_stress_all has 1 failures.
  - 19.kmac_stress_all.71862894673222910641158556641775650589493071924607491798244372929177832812864
    Line 997, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 884462385296 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 884462385296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 2 failures:
- Test kmac_stress_all_with_rand_reset has 2 failures.
  - 3.kmac_stress_all_with_rand_reset.93088637216629965421781883733483579892844070971691219538746812984049060880100
    Line 658, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8601641415 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483680 [0x80000020]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 8601641415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.kmac_stress_all_with_rand_reset.113918821767244080366918194813267166312389230584651346432914560310268918432502
    Line 2263, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 70043922491 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483664 [0x80000010]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 70043922491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 2 failures:
- Test kmac_entropy_refresh has 1 failures.
  - 30.kmac_entropy_refresh.13515410938066514017965722747548933200130864802736867604936725710878697540055
    Line 535, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/30.kmac_entropy_refresh/latest/run.log
```
  UVM_FATAL @ 23736698182 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (157 [0x9d] vs 50 [0x32]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 23736698182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_stress_all has 1 failures.
  - 42.kmac_stress_all.111798295121583391153511402891057948806051771040546794490325491822015194855683
    Line 639, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/42.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 3754684603 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (43 [0x2b] vs 220 [0xdc]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 3754684603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 2 failures:
- Test kmac_test_vectors_sha3_224 has 1 failures.
  - 32.kmac_test_vectors_sha3_224.106969063252893883320044283494689870626007912909006158282745037117441602059490
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/32.kmac_test_vectors_sha3_224/latest/run.log
```
  UVM_ERROR @  82171262 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  82171262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_shake_128 has 1 failures.
  - 33.kmac_test_vectors_shake_128.93896626078358629301375630044604187116792146523098430686091934472386108799041
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/33.kmac_test_vectors_shake_128/latest/run.log
```
  UVM_ERROR @  43717653 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  43717653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job kmac_masked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test kmac_long_msg_and_output has 1 failures.
  - 16.kmac_long_msg_and_output.89063728790691717979078723195959323138658098675929094816917797598927269830207
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/16.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:eb975c43-83dc-4dcd-9196-a74281580b7d
```