KMAC/MASKED Simulation Results

Tuesday June 11 2024 19:02:38 UTC

GitHub Revision: `dd5ad5fb77`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 66418170746903624595625818392428707033482455256751560525176982524210226376736

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.762m	27.989ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.210s	44.161us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.240s	26.742us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	18.490s	2.009ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	8.180s	518.516us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.610s	80.817us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.240s	26.742us	20	20	100.00
		kmac_csr_aliasing	8.180s	518.516us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.830s	13.964us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.420s	67.320us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	51.082m	29.739ms	50	50	100.00
V2	burst_write	kmac_burst_write	29.318m	18.580ms	48	50	96.00
V2	test_vectors	kmac_test_vectors_sha3_224	48.169m	1.659s	49	50	98.00
		kmac_test_vectors_sha3_256	39.169m	406.318ms	49	50	98.00
		kmac_test_vectors_sha3_384	32.654m	280.735ms	50	50	100.00
		kmac_test_vectors_sha3_512	25.114m	414.201ms	50	50	100.00
		kmac_test_vectors_shake_128	1.900h	1.007s	49	50	98.00
		kmac_test_vectors_shake_256	1.836h	3.657s	49	50	98.00
		kmac_test_vectors_kmac	7.690s	3.180ms	50	50	100.00
		kmac_test_vectors_kmac_xof	7.600s	689.121us	50	50	100.00
V2	sideload	kmac_sideload	8.808m	22.978ms	50	50	100.00
V2	app	kmac_app	6.609m	12.586ms	48	50	96.00
V2	app_with_partial_data	kmac_app_with_partial_data	7.516m	19.925ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	7.577m	16.072ms	49	50	98.00
V2	error	kmac_error	8.336m	5.605ms	45	50	90.00
V2	key_error	kmac_key_error	17.870s	20.129ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	43.910s	645.862us	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	30.800s	998.955us	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.220m	7.303ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	53.080s	1.615ms	50	50	100.00
V2	stress_all	kmac_stress_all	52.534m	417.653ms	47	50	94.00
V2	intr_test	kmac_intr_test	0.900s	49.558us	50	50	100.00
V2	alert_test	kmac_alert_test	0.990s	59.312us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.490s	341.159us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.490s	341.159us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.210s	44.161us	5	5	100.00
		kmac_csr_rw	1.240s	26.742us	20	20	100.00
		kmac_csr_aliasing	8.180s	518.516us	5	5	100.00
		kmac_same_csr_outstanding	2.910s	253.785us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.210s	44.161us	5	5	100.00
		kmac_csr_rw	1.240s	26.742us	20	20	100.00
		kmac_csr_aliasing	8.180s	518.516us	5	5	100.00
		kmac_same_csr_outstanding	2.910s	253.785us	20	20	100.00
V2		TOTAL			1033	1050	98.38
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.560s	194.249us	19	20	95.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.560s	194.249us	19	20	95.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.560s	194.249us	19	20	95.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.560s	194.249us	19	20	95.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.040s	159.486us	15	20	75.00
V2S	tl_intg_err	kmac_sec_cm	1.848m	11.859ms	5	5	100.00
		kmac_tl_intg_err	5.060s	722.783us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.060s	722.783us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	53.080s	1.615ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.762m	27.989ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	8.808m	22.978ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.560s	194.249us	19	20	95.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.848m	11.859ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.848m	11.859ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.848m	11.859ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.762m	27.989ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	53.080s	1.615ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.848m	11.859ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.429m	120.487ms	9	10	90.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.762m	27.989ms	50	50	100.00
V2S		TOTAL			68	75	90.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	56.925m	371.123ms	15	50	30.00
V3		TOTAL			15	50	30.00
		TOTAL			1231	1290	95.43

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	16	64.00
V2S	5	5	2	40.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.10	97.89	92.55	99.89	76.06	95.53	98.89	97.88

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 24 failures:
- Test kmac_stress_all_with_rand_reset has 24 failures.
  - 0.kmac_stress_all_with_rand_reset.3675227607705021258071950952608454417414296216849448612407717851790477937612
    Line 540, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 79184152674 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 79184152674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.92830576283253803087672451664468708801960904538458922557429354331477803329077
    Line 1479, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 35034425923 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 35034425923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 22 more failures.
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 9 failures:
- Test kmac_stress_all_with_rand_reset has 9 failures.
  - 5.kmac_stress_all_with_rand_reset.18055097486994250528591501417270552273704640398995738234186865873820131484938
    Line 1127, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 19582047023 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483648 [0x80000000]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 19582047023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 12.kmac_stress_all_with_rand_reset.87199920115699724823387072807896270461689576555995738290681214521655672535516
    Line 531, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/12.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 13181125462 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483656 [0x80000008]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 13181125462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: * Check_csr_read_clear_staged_val task: check update_err status has 6 failures:

Test kmac_shadow_reg_errors_with_csr_rw has 5 failures.

2.kmac_shadow_reg_errors_with_csr_rw.51166142403265935539912241217970661464181701434934494482566497850320012664273
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  97818836 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  97818836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.kmac_shadow_reg_errors_with_csr_rw.1159631997832357367759575355414737902986444137710649144775422719452387875595
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  20930532 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  20930532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test kmac_shadow_reg_errors has 1 failures.

11.kmac_shadow_reg_errors.27151574880667625668892684263426371691831170993132309062240209725614717899543
Line 255, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @  18731322 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  18731322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 6 failures:
- Test kmac_error has 4 failures.
  - 3.kmac_error.94938559228056106914723123065492647673002652466223109848955619199265024674035
    Line 402, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_error/latest/run.log
```
  UVM_FATAL @ 10286589912 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 10286589912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 22.kmac_error.77595289365186163567342638046904419112248104282148663372317152711288785014308
    Line 446, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/22.kmac_error/latest/run.log
```
  UVM_FATAL @ 10198965662 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 10198965662 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
- Test kmac_stress_all_with_rand_reset has 2 failures.
  - 7.kmac_stress_all_with_rand_reset.106218357913015895663082083587785433557109876393657755638921874891162575272638
    Line 3400, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 293435476869 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 293435476869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 38.kmac_stress_all_with_rand_reset.40908235212916690768335996502586555858401910754687974783185072550685124698437
    Line 592, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/38.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 14039120050 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 14039120050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 5 failures:

Test kmac_mubi has 1 failures.

2.kmac_mubi.23157621458676241819334902310258330876229978985021460144588760033634372222674
Line 817, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_mubi/latest/run.log

  UVM_FATAL @ 10291621028 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (178 [0xb2] vs 51 [0x33]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 10291621028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app has 2 failures.

14.kmac_app.58410293014289961886309813094308600140441202061904513639651781974687956167720
Line 859, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_app/latest/run.log

  UVM_FATAL @ 15524640253 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (190 [0xbe] vs 181 [0xb5]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 15524640253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

39.kmac_app.77365955851152319456130434643152320601430932321899181085215138620542449768341
Line 349, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/39.kmac_app/latest/run.log

  UVM_FATAL @ 1712982182 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (231 [0xe7] vs 126 [0x7e]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 1712982182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 2 failures.

45.kmac_stress_all.41261065204761475927083517822077913197552429013927907005422945524017794892416
Line 635, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/45.kmac_stress_all/latest/run.log

  UVM_FATAL @ 13315183108 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (236 [0xec] vs 83 [0x53]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 13315183108 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

47.kmac_stress_all.58691349693574223243065585655773004685784669401718258523490136100937134330048
Line 885, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/47.kmac_stress_all/latest/run.log

  UVM_FATAL @ 46822445524 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (222 [0xde] vs 189 [0xbd]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 46822445524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 5 failures:
- Test kmac_entropy_refresh has 1 failures.
  - 10.kmac_entropy_refresh.50772022687037611482329012484241616242335289965885152058451086484060005446248
    Line 296, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/10.kmac_entropy_refresh/latest/run.log
```
  UVM_ERROR @ 776890381 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 776890381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_stress_all has 1 failures.
  - 22.kmac_stress_all.37393089367101054835142486904224682357595849380767634805456032665032285861668
    Line 1572, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/22.kmac_stress_all/latest/run.log
```
  UVM_ERROR @ 202573662639 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 202573662639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_sha3_224 has 1 failures.
  - 24.kmac_test_vectors_sha3_224.62553681403023976087823353762437838256929136226893300457650507546841144568496
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/24.kmac_test_vectors_sha3_224/latest/run.log
```
  UVM_ERROR @  47723135 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  47723135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_shake_256 has 1 failures.
  - 29.kmac_test_vectors_shake_256.18125753954872965015557803792877687029231374284762605544765204186521893656120
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/29.kmac_test_vectors_shake_256/latest/run.log
```
  UVM_ERROR @ 114046578 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 114046578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_sha3_256 has 1 failures.
  - 45.kmac_test_vectors_sha3_256.102751471859369066273234075732625918964004264092649328802822539310354619020185
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/45.kmac_test_vectors_sha3_256/latest/run.log
```
  UVM_ERROR @ 210688260 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 210688260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
- Test kmac_burst_write has 2 failures.
  - 5.kmac_burst_write.103895541318064768513824232775506022396586938285883884971208168628687503316912
    Line 758, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 16.kmac_burst_write.72660994038981019580108673669021919385116425306829311850210439039296778484525
    Line 1136, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/16.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_shake_128 has 1 failures.
  - 20.kmac_test_vectors_shake_128.32662940447140712425580607969460039107672161996182935384357011123167273955647
    Line 6020, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/20.kmac_test_vectors_shake_128/latest/run.log
```
  UVM_FATAL @ 5000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 5000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 5000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_error has 1 failures.
  - 29.kmac_error.14648262819316227854132566402775453450116769897590718312009832013132000506853
    Line 792, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/29.kmac_error/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```