KMAC/MASKED Simulation Results

Saturday June 22 2024 23:02:20 UTC

GitHub Revision: `8fdb25c8d9`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 116774179587740886356693500529232784059703555433764635649168222249757162669

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.607m	9.779ms	49	50	98.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.130s	154.225us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.250s	33.295us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	21.810s	9.000ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.700s	1.835ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.710s	132.778us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.250s	33.295us	20	20	100.00
		kmac_csr_aliasing	9.700s	1.835ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.770s	122.236us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.610s	407.741us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	long_msg_and_output	kmac_long_msg_and_output	56.929m	91.862ms	50	50	100.00
V2	burst_write	kmac_burst_write	28.595m	63.036ms	47	50	94.00
V2	test_vectors	kmac_test_vectors_sha3_224	44.795m	397.731ms	50	50	100.00
		kmac_test_vectors_sha3_256	43.677m	1.309s	49	50	98.00
		kmac_test_vectors_sha3_384	33.196m	538.235ms	50	50	100.00
		kmac_test_vectors_sha3_512	24.158m	259.784ms	50	50	100.00
		kmac_test_vectors_shake_128	1.852h	1.540s	50	50	100.00
		kmac_test_vectors_shake_256	1.562h	792.970ms	50	50	100.00
		kmac_test_vectors_kmac	7.460s	3.514ms	50	50	100.00
		kmac_test_vectors_kmac_xof	7.360s	1.096ms	49	50	98.00
V2	sideload	kmac_sideload	8.469m	114.136ms	50	50	100.00
V2	app	kmac_app	6.917m	13.287ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.705m	200.000ms	9	10	90.00
V2	entropy_refresh	kmac_entropy_refresh	7.524m	22.452ms	50	50	100.00
V2	error	kmac_error	6.991m	33.470ms	48	50	96.00
V2	key_error	kmac_key_error	17.870s	15.711ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	45.840s	1.276ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	33.250s	451.772us	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	48.990s	9.789ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	18.670s	1.371ms	50	50	100.00
V2	stress_all	kmac_stress_all	51.162m	116.455ms	49	50	98.00
V2	intr_test	kmac_intr_test	0.900s	99.918us	50	50	100.00
V2	alert_test	kmac_alert_test	0.960s	334.502us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.290s	452.826us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.290s	452.826us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.130s	154.225us	5	5	100.00
		kmac_csr_rw	1.250s	33.295us	20	20	100.00
		kmac_csr_aliasing	9.700s	1.835ms	5	5	100.00
		kmac_same_csr_outstanding	3.240s	1.773ms	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.130s	154.225us	5	5	100.00
		kmac_csr_rw	1.250s	33.295us	20	20	100.00
		kmac_csr_aliasing	9.700s	1.835ms	5	5	100.00
		kmac_same_csr_outstanding	3.240s	1.773ms	20	20	100.00
V2		TOTAL			1040	1050	99.05
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.640s	115.680us	16	20	80.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.640s	115.680us	16	20	80.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.640s	115.680us	16	20	80.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.640s	115.680us	16	20	80.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.220s	483.702us	18	20	90.00
V2S	tl_intg_err	kmac_sec_cm	1.981m	8.901ms	5	5	100.00
		kmac_tl_intg_err	4.920s	242.333us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.920s	242.333us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	18.670s	1.371ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.607m	9.779ms	49	50	98.00
V2S	sec_cm_key_sideload	kmac_sideload	8.469m	114.136ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.640s	115.680us	16	20	80.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.981m	8.901ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.981m	8.901ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.981m	8.901ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.607m	9.779ms	49	50	98.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	18.670s	1.371ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.981m	8.901ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	7.651m	18.504ms	9	10	90.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.607m	9.779ms	49	50	98.00
V2S		TOTAL			68	75	90.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	38.117m	78.023ms	5	10	50.00
V3		TOTAL			5	10	50.00
		TOTAL			1227	1250	98.16

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	25	25	18	72.00
V2S	5	5	2	40.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.24	97.91	92.62	99.89	76.76	95.59	99.05	97.88

Failure Buckets

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: * Check_csr_read_clear_staged_val task: check update_err status has 6 failures:

Test kmac_shadow_reg_errors has 4 failures.

0.kmac_shadow_reg_errors.38825908402982470552482476166872981894435889944031377606607587023974672860802
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @  14987374 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  14987374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.kmac_shadow_reg_errors.86590755018820562621092775862112478100745876788281339451077900514111277002297
Line 255, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @  15907407 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  15907407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test kmac_shadow_reg_errors_with_csr_rw has 2 failures.

11.kmac_shadow_reg_errors_with_csr_rw.36243833496957355669811518442844215111374702806334445549467717522056610102380
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  87048482 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  87048482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

15.kmac_shadow_reg_errors_with_csr_rw.51391247013441921845310598703123159600244231468000732774326733378982974381066
Line 255, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/15.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  53447719 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  53447719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 6 failures:
- Test kmac_app_with_partial_data has 1 failures.
  - 2.kmac_app_with_partial_data.90083719360456899970783635036317335206492449346965931206884626874197527804346
    Line 858, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_app_with_partial_data/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_mubi has 1 failures.
  - 5.kmac_mubi.92447056906637606491364853955940604778103834607546896484802265097153522745542
    Line 1064, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_mubi/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_burst_write has 3 failures.
  - 6.kmac_burst_write.77627843683403886263574805780725379350294790690786109453888879240478636728136
    Line 1112, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 18.kmac_burst_write.77572524395563250224562907625032463884504912153515427421376663050542583380625
    Line 572, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/18.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test kmac_app has 1 failures.
  - 8.kmac_app.82197682913867735590234720571646805392421095279251614687614715225151960308507
    Line 948, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_app/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 4 failures:
- Test kmac_smoke has 1 failures.
  - 0.kmac_smoke.78759794470081965542084617268013768815358394281649678675299253045412248178211
    Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_smoke/latest/run.log
```
  UVM_ERROR @  58571260 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  58571260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_kmac_xof has 1 failures.
  - 5.kmac_test_vectors_kmac_xof.80374236177589356802596132333770306387356697035118880846903375348189803550539
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_test_vectors_kmac_xof/latest/run.log
```
  UVM_ERROR @  93591632 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  93591632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_sha3_256 has 1 failures.
  - 43.kmac_test_vectors_sha3_256.17368955513306174675559686279252464900233208849002020245002728093915833674141
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/43.kmac_test_vectors_sha3_256/latest/run.log
```
  UVM_ERROR @  30997863 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  30997863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_stress_all has 1 failures.
  - 45.kmac_stress_all.113886351834066417999511604504655854183044635449411460128416844422042219345195
    Line 1442, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/45.kmac_stress_all/latest/run.log
```
  UVM_ERROR @ 25619696853 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 25619696853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:828) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
- Test kmac_stress_all_with_rand_reset has 3 failures.
  - 1.kmac_stress_all_with_rand_reset.38186342566155539008195415595086626741588540600360269656919539793215525439292
    Line 462, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 28984742453 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 28984742453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.kmac_stress_all_with_rand_reset.29290631001752787662950642772347126810702139187325794758944160390996874393676
    Line 634, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 18266063398 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 18266063398 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 2 failures:
- Test kmac_stress_all_with_rand_reset has 2 failures.
  - 2.kmac_stress_all_with_rand_reset.60101750815085522386777409073454175884581536591930854136555883316222426967715
    Line 1534, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 106906175121 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483728 [0x80000050]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 106906175121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.kmac_stress_all_with_rand_reset.48107349736067402779585163972116400729934967431494825575805782522920225475548
    Line 929, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 109424386287 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483664 [0x80000010]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 109424386287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 2 failures:
- Test kmac_error has 2 failures.
  - 37.kmac_error.88628623557036173835606099948295208669565656220553652504907102518311279373067
    Line 756, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/37.kmac_error/latest/run.log
```
  UVM_FATAL @ 10071031266 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 10071031266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 42.kmac_error.103860995196477372053365305661479886962189328793743865364342748536064821596943
    Line 441, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/42.kmac_error/latest/run.log
```
  UVM_FATAL @ 10347058248 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 10347058248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```