KMAC/MASKED Simulation Results

Sunday June 09 2024 19:02:32 UTC

GitHub Revision: `f92a5ee77b`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 74888572473032497941251936200792687439223302665780333354656685678472336958420

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.494m	8.387ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.190s	63.648us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.280s	34.396us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	21.360s	1.478ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.460s	384.251us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.690s	500.527us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.280s	34.396us	20	20	100.00
		kmac_csr_aliasing	9.460s	384.251us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.780s	13.321us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.490s	37.717us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	56.722m	30.748ms	49	50	98.00
V2	burst_write	kmac_burst_write	27.661m	12.754ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	42.389m	285.078ms	49	50	98.00
		kmac_test_vectors_sha3_256	41.558m	1.502s	49	50	98.00
		kmac_test_vectors_sha3_384	33.751m	348.679ms	47	50	94.00
		kmac_test_vectors_sha3_512	24.909m	557.235ms	50	50	100.00
		kmac_test_vectors_shake_128	1.843h	1.065s	49	50	98.00
		kmac_test_vectors_shake_256	1.732h	2.730s	50	50	100.00
		kmac_test_vectors_kmac	7.590s	1.568ms	49	50	98.00
		kmac_test_vectors_kmac_xof	7.110s	4.696ms	50	50	100.00
V2	sideload	kmac_sideload	8.803m	21.818ms	50	50	100.00
V2	app	kmac_app	6.903m	17.966ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	3.967m	8.593ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	7.601m	43.137ms	49	50	98.00
V2	error	kmac_error	8.739m	133.763ms	50	50	100.00
V2	key_error	kmac_key_error	17.020s	25.702ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	54.930s	583.204us	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	58.290s	7.466ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	46.850s	12.319ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	45.880s	7.408ms	50	50	100.00
V2	stress_all	kmac_stress_all	45.217m	79.415ms	48	50	96.00
V2	intr_test	kmac_intr_test	0.930s	22.841us	50	50	100.00
V2	alert_test	kmac_alert_test	0.930s	46.904us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.320s	195.454us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.320s	195.454us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.190s	63.648us	5	5	100.00
		kmac_csr_rw	1.280s	34.396us	20	20	100.00
		kmac_csr_aliasing	9.460s	384.251us	5	5	100.00
		kmac_same_csr_outstanding	2.890s	1.171ms	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.190s	63.648us	5	5	100.00
		kmac_csr_rw	1.280s	34.396us	20	20	100.00
		kmac_csr_aliasing	9.460s	384.251us	5	5	100.00
		kmac_same_csr_outstanding	2.890s	1.171ms	20	20	100.00
V2		TOTAL			1038	1050	98.86
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.550s	72.075us	18	20	90.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.550s	72.075us	18	20	90.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.550s	72.075us	18	20	90.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.550s	72.075us	18	20	90.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.770s	122.713us	17	20	85.00
V2S	tl_intg_err	kmac_sec_cm	1.969m	8.816ms	5	5	100.00
		kmac_tl_intg_err	5.850s	2.320ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.850s	2.320ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	45.880s	7.408ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.494m	8.387ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	8.803m	21.818ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.550s	72.075us	18	20	90.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.969m	8.816ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.969m	8.816ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.969m	8.816ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.494m	8.387ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	45.880s	7.408ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.969m	8.816ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.797m	12.577ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.494m	8.387ms	50	50	100.00
V2S		TOTAL			70	75	93.33
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.041h	189.632ms	19	50	38.00
V3		TOTAL			19	50	38.00
		TOTAL			1242	1290	96.28

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	16	64.00
V2S	5	5	3	60.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.41	97.89	92.62	99.89	78.17	95.53	98.89	97.88

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 25 failures:
- Test kmac_stress_all_with_rand_reset has 25 failures.
  - 0.kmac_stress_all_with_rand_reset.3526750749646565828244347931291035572766840478936814210862547131094482387203
    Line 1185, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 266853039996 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 266853039996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.kmac_stress_all_with_rand_reset.92537376351575216409503170133013332051635653089540665777736230259454580414245
    Line 2662, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 67700588791 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 67700588791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 23 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 7 failures:
- Test kmac_test_vectors_sha3_256 has 1 failures.
  - 0.kmac_test_vectors_sha3_256.41355647291080193223349748123190290782066775586924059955738003996743741931076
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_256/latest/run.log
```
  UVM_ERROR @  33971251 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  33971251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_kmac has 1 failures.
  - 3.kmac_test_vectors_kmac.45777838109584903109893199226661271994175716347547413590443254998152302674640
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_test_vectors_kmac/latest/run.log
```
  UVM_ERROR @  78768868 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  78768868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_sha3_384 has 3 failures.
  - 8.kmac_test_vectors_sha3_384.100587467503134815712717504988360993972471546190181189788866139273316014224440
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_test_vectors_sha3_384/latest/run.log
```
  UVM_ERROR @  31695647 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  31695647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 10.kmac_test_vectors_sha3_384.97254677590223835198976778553177557715449848419092741391901848135325718328651
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/10.kmac_test_vectors_sha3_384/latest/run.log
```
  UVM_ERROR @ 161154382 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 161154382 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test kmac_test_vectors_shake_128 has 1 failures.
  - 24.kmac_test_vectors_shake_128.89786806415434579200593105087140665995893889301940999112872235983202680852976
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/24.kmac_test_vectors_shake_128/latest/run.log
```
  UVM_ERROR @ 270415461 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 270415461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_sha3_224 has 1 failures.
  - 25.kmac_test_vectors_sha3_224.114503217433197839794046566261983407677070903736743057031182960234733993730069
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/25.kmac_test_vectors_sha3_224/latest/run.log
```
  UVM_ERROR @ 193825661 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 193825661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 5 failures:
- Test kmac_stress_all_with_rand_reset has 5 failures.
  - 4.kmac_stress_all_with_rand_reset.107540414982399983762948502077061107409679121957147629403621966731715785214390
    Line 1516, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 174456591998 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483664 [0x80000010]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 174456591998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 14.kmac_stress_all_with_rand_reset.58982743743600644967389240991316488062288570653838322574291508111525578069491
    Line 569, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 12849308537 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483728 [0x80000050]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 12849308537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: * Check_csr_read_clear_staged_val task: check update_err status has 5 failures:

Test kmac_shadow_reg_errors_with_csr_rw has 3 failures.

5.kmac_shadow_reg_errors_with_csr_rw.49428635817640089728345311640278272312558276927902528596218510551983704088598
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @   6094813 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @   6094813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.kmac_shadow_reg_errors_with_csr_rw.99288638381932809266268474013936934088783801346664841151568536712586839483467
Line 255, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @ 265994388 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @ 265994388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test kmac_shadow_reg_errors has 2 failures.

11.kmac_shadow_reg_errors.24724277867747926579413933881599323547219024135604552961717022367615318037169
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @   9405816 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @   9405816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

18.kmac_shadow_reg_errors.4531554026243669275253573572167165519933576425664581910444097555832921274834
Line 255, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/18.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @  54931697 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  54931697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 3 failures:
- Test kmac_stress_all has 2 failures.
  - 12.kmac_stress_all.112560127705067349092148191291915951490097313462570413726731256335424418739422
    Line 568, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/12.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 83943138481 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 83943138481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 14.kmac_stress_all.33961811693599531573171975629076713143111599620153779009409631866772134019637
    Line 308, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 14871893156 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 14871893156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 15.kmac_stress_all_with_rand_reset.65522732529017405216916047367967287220268104339473930178756216621074607820670
    Line 641, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/15.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 18893842408 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 18893842408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job kmac_masked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test kmac_long_msg_and_output has 1 failures.
  - 1.kmac_long_msg_and_output.67666118387003123359070553059115643922738933105036008610040035119653491042835
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:a1058f02-3cb3-4221-bd10-85461be287c0
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_burst_write has 1 failures.
  - 15.kmac_burst_write.74541417192490076762133928749995712923896034729221544733995626897558823145326
    Line 758, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/15.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 1 failures:
- Test kmac_entropy_refresh has 1 failures.
  - 36.kmac_entropy_refresh.105133461222626492325691754646168209430936742740916701997056090201802628150953
    Line 327, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/36.kmac_entropy_refresh/latest/run.log
```
  UVM_FATAL @ 12399158146 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (233 [0xe9] vs 29 [0x1d]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 12399158146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```