KMAC/MASKED Simulation Results

Tuesday June 25 2024 23:02:40 UTC

GitHub Revision: `3fd3528c8c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 44317642457786780768002458033256869318159334982704173107202396839344093642292

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.467m	17.172ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.180s	91.015us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.260s	74.169us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	20.340s	1.269ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.660s	2.109ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.730s	183.808us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.260s	74.169us	20	20	100.00
		kmac_csr_aliasing	9.660s	2.109ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.800s	27.501us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.590s	146.856us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	56.854m	242.082ms	50	50	100.00
V2	burst_write	kmac_burst_write	26.298m	51.531ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	46.297m	1.687s	50	50	100.00
		kmac_test_vectors_sha3_256	41.081m	926.685ms	50	50	100.00
		kmac_test_vectors_sha3_384	30.872m	138.576ms	50	50	100.00
		kmac_test_vectors_sha3_512	25.166m	621.632ms	49	50	98.00
		kmac_test_vectors_shake_128	1.888h	3.709s	49	50	98.00
		kmac_test_vectors_shake_256	1.518h	335.580ms	50	50	100.00
		kmac_test_vectors_kmac	7.270s	1.019ms	50	50	100.00
		kmac_test_vectors_kmac_xof	7.370s	333.403us	50	50	100.00
V2	sideload	kmac_sideload	8.945m	44.525ms	50	50	100.00
V2	app	kmac_app	7.251m	39.248ms	46	50	92.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.421m	14.990ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	7.542m	16.231ms	50	50	100.00
V2	error	kmac_error	9.392m	90.127ms	48	50	96.00
V2	key_error	kmac_key_error	13.950s	8.750ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	47.250s	3.640ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	52.910s	2.217ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.126m	6.405ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	1.009m	5.867ms	50	50	100.00
V2	stress_all	kmac_stress_all	51.072m	30.766ms	43	50	86.00
V2	intr_test	kmac_intr_test	0.900s	19.017us	50	50	100.00
V2	alert_test	kmac_alert_test	0.980s	143.002us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.410s	133.739us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.410s	133.739us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.180s	91.015us	5	5	100.00
		kmac_csr_rw	1.260s	74.169us	20	20	100.00
		kmac_csr_aliasing	9.660s	2.109ms	5	5	100.00
		kmac_same_csr_outstanding	2.760s	448.468us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.180s	91.015us	5	5	100.00
		kmac_csr_rw	1.260s	74.169us	20	20	100.00
		kmac_csr_aliasing	9.660s	2.109ms	5	5	100.00
		kmac_same_csr_outstanding	2.760s	448.468us	20	20	100.00
V2		TOTAL			1035	1050	98.57
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.520s	632.915us	19	20	95.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.520s	632.915us	19	20	95.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.520s	632.915us	19	20	95.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.520s	632.915us	19	20	95.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.180s	327.434us	16	20	80.00
V2S	tl_intg_err	kmac_sec_cm	1.375m	5.150ms	5	5	100.00
		kmac_tl_intg_err	5.960s	3.646ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.960s	3.646ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.009m	5.867ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.467m	17.172ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	8.945m	44.525ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.520s	632.915us	19	20	95.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.375m	5.150ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.375m	5.150ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.375m	5.150ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.467m	17.172ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.009m	5.867ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.375m	5.150ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.209m	50.251ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.467m	17.172ms	50	50	100.00
V2S		TOTAL			70	75	93.33
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	23.447m	21.821ms	1	10	10.00
V3		TOTAL			1	10	10.00
		TOTAL			1221	1250	97.68

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	20	80.00
V2S	5	5	3	60.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.25	97.91	92.68	99.89	76.76	95.59	99.05	97.88

Failure Buckets

UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 7 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 0.kmac_stress_all_with_rand_reset.28336496282426938690623765688655382821503281984181757584136115150160645774905
    Line 1284, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 21820653128 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 21820653128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_stress_all has 5 failures.
  - 5.kmac_stress_all.65152325673810351730801871676658703426040909315563606165100231586866166016179
    Line 1152, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 202333219951 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 202333219951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.kmac_stress_all.86929616183815038193269432887928099522853487834509880423320231040283742476185
    Line 1679, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 290773836931 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 290773836931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
- Test kmac_error has 1 failures.
  - 20.kmac_error.52311714019620786511548582196816093283412322392083874171586183448744777387902
    Line 720, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/20.kmac_error/latest/run.log
```
  UVM_FATAL @ 10107717013 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 10107717013 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:828) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 5 failures:
- Test kmac_stress_all_with_rand_reset has 5 failures.
  - 1.kmac_stress_all_with_rand_reset.35572990270612966430218479938655824630351501692820378823969266593477891936052
    Line 360, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 24739179234 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 24739179234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.kmac_stress_all_with_rand_reset.62136650875648134297621339087036989952300009481214076036992484343959732603414
    Line 1332, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 43230528244 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 43230528244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: * Check_csr_read_clear_staged_val task: check update_err status has 5 failures:

Test kmac_shadow_reg_errors_with_csr_rw has 4 failures.

7.kmac_shadow_reg_errors_with_csr_rw.97542635812839837370891521630062303084234733759806601926148178696435272966601
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  16016663 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  16016663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

12.kmac_shadow_reg_errors_with_csr_rw.33492527143176996872024226721508746955981474132957835290971660471414866641863
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/12.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  99374571 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  99374571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test kmac_shadow_reg_errors has 1 failures.

10.kmac_shadow_reg_errors.59992734251695104844519263585714765521157894683735425128205022016806406489202
Line 255, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/10.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @  12362611 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  12362611 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 4 failures:

Test kmac_app has 4 failures.

0.kmac_app.98514238654529448579874421366579009268538376357608853775378235024965656490614
Line 257, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_app/latest/run.log

  UVM_FATAL @ 1169123787 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (97 [0x61] vs 233 [0xe9]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 1169123787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

40.kmac_app.45807581728421336183109756419613513698891160347924150044370993425893403602372
Line 299, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/40.kmac_app/latest/run.log

  UVM_FATAL @ 985232942 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (221 [0xdd] vs 223 [0xdf]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 985232942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 3 failures:
- Test kmac_test_vectors_sha3_512 has 1 failures.
  - 4.kmac_test_vectors_sha3_512.107369836188651267069603137373836273611506553871008957457930209645992572406060
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_512/latest/run.log
```
  UVM_ERROR @  31819414 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  31819414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_stress_all has 2 failures.
  - 30.kmac_stress_all.14405642472472198686316112044242342188584604622372002292281605097457913048952
    Line 1131, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/30.kmac_stress_all/latest/run.log
```
  UVM_ERROR @ 38358405681 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 38358405681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 31.kmac_stress_all.42710427692483180831343946014132389393103002431296080102144498634567368396153
    Line 601, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/31.kmac_stress_all/latest/run.log
```
  UVM_ERROR @ 25090823599 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 25090823599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 3 failures:
- Test kmac_stress_all_with_rand_reset has 3 failures.
  - 5.kmac_stress_all_with_rand_reset.83869149803026634086289208149158247706587173352002788366300798817887981659170
    Line 263, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 127735586 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483752 [0x80000068]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 127735586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.kmac_stress_all_with_rand_reset.43237716126834199503397401036471829173828293632808733425463213358658373823763
    Line 750, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 40870166843 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483752 [0x80000068]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 40870166843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_error has 1 failures.
  - 23.kmac_error.9754164016665940228285608626224015236550338397607886421475995148716622109461
    Line 848, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/23.kmac_error/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job kmac_masked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test kmac_test_vectors_shake_128 has 1 failures.
  - 25.kmac_test_vectors_shake_128.70937907899798600647006060665312767310085400583641702537349294879454153386149
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/25.kmac_test_vectors_shake_128/latest/run.log
```
  Job ID: smart:44b46955-c4dc-41ce-810c-dba7005b7ee2
```