KMAC/MASKED Simulation Results

Wednesday June 26 2024 23:02:36 UTC

GitHub Revision: `be1c4a4f52`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 44766564427213563291105655232733134394512207819884794315335669279596867428010

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.487m	12.133ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.190s	43.477us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.260s	36.619us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	22.930s	6.018ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	5.340s	497.366us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.600s	265.550us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.260s	36.619us	20	20	100.00
		kmac_csr_aliasing	5.340s	497.366us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.810s	19.124us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.500s	132.918us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	55.276m	128.234ms	49	50	98.00
V2	burst_write	kmac_burst_write	26.210m	16.069ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	43.755m	404.136ms	49	50	98.00
		kmac_test_vectors_sha3_256	40.106m	529.678ms	50	50	100.00
		kmac_test_vectors_sha3_384	31.538m	300.596ms	50	50	100.00
		kmac_test_vectors_sha3_512	23.806m	154.190ms	50	50	100.00
		kmac_test_vectors_shake_128	1.866h	1.080s	49	50	98.00
		kmac_test_vectors_shake_256	1.664h	1.671s	49	50	98.00
		kmac_test_vectors_kmac	8.630s	880.671us	49	50	98.00
		kmac_test_vectors_kmac_xof	7.190s	347.174us	49	50	98.00
V2	sideload	kmac_sideload	8.557m	79.485ms	50	50	100.00
V2	app	kmac_app	6.930m	9.310ms	48	50	96.00
V2	app_with_partial_data	kmac_app_with_partial_data	7.071m	81.534ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	7.067m	31.925ms	46	50	92.00
V2	error	kmac_error	8.784m	62.077ms	48	50	96.00
V2	key_error	kmac_key_error	14.890s	7.492ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	55.200s	8.759ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	15.220s	669.088us	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.411m	58.756ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	57.240s	5.866ms	50	50	100.00
V2	stress_all	kmac_stress_all	59.486m	216.043ms	47	50	94.00
V2	intr_test	kmac_intr_test	0.890s	19.642us	50	50	100.00
V2	alert_test	kmac_alert_test	0.880s	64.707us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.270s	112.978us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.270s	112.978us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.190s	43.477us	5	5	100.00
		kmac_csr_rw	1.260s	36.619us	20	20	100.00
		kmac_csr_aliasing	5.340s	497.366us	5	5	100.00
		kmac_same_csr_outstanding	2.890s	1.251ms	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.190s	43.477us	5	5	100.00
		kmac_csr_rw	1.260s	36.619us	20	20	100.00
		kmac_csr_aliasing	5.340s	497.366us	5	5	100.00
		kmac_same_csr_outstanding	2.890s	1.251ms	20	20	100.00
V2		TOTAL			1032	1050	98.29
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.500s	212.119us	18	20	90.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.500s	212.119us	18	20	90.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.500s	212.119us	18	20	90.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.500s	212.119us	18	20	90.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.060s	782.748us	17	20	85.00
V2S	tl_intg_err	kmac_sec_cm	1.493m	37.409ms	5	5	100.00
		kmac_tl_intg_err	5.620s	341.067us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.620s	341.067us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	57.240s	5.866ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.487m	12.133ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	8.557m	79.485ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.500s	212.119us	18	20	90.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.493m	37.409ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.493m	37.409ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.493m	37.409ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.487m	12.133ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	57.240s	5.866ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.493m	37.409ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.800m	81.533ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.487m	12.133ms	50	50	100.00
V2S		TOTAL			70	75	93.33
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	46.162m	73.261ms	2	10	20.00
V3		TOTAL			2	10	20.00
		TOTAL			1219	1250	97.52

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	14	56.00
V2S	5	5	3	60.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.24	97.91	92.62	99.89	76.76	95.59	99.05	97.88

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 7 failures:
- Test kmac_stress_all_with_rand_reset has 7 failures.
  - 0.kmac_stress_all_with_rand_reset.23326933971995775432348820949943100020516318547360826567908005099766859280207
    Line 464, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3317327823 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3317327823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.15421014583587808885246556111997555007297580928284597905521811200742875501849
    Line 2505, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 64384012494 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 64384012494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: * Check_csr_read_clear_staged_val task: check update_err status has 5 failures:

Test kmac_shadow_reg_errors_with_csr_rw has 3 failures.

1.kmac_shadow_reg_errors_with_csr_rw.93788897515106739293530382433238870041223302996474598877512148981063279436089
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  12486055 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  12486055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.kmac_shadow_reg_errors_with_csr_rw.93987137673369083140535924385474253816621182603586606051057608293502429650511
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  51584925 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  51584925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test kmac_shadow_reg_errors has 2 failures.

7.kmac_shadow_reg_errors.17411160944998757992507601055487570496126013022090812722889903945139329341880
Line 255, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @  41840991 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  41840991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.kmac_shadow_reg_errors.23242526997783431717189806122765120716683812075085984936142808385289448939085
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @   4858026 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @   4858026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 5 failures:

Test kmac_stress_all has 1 failures.

4.kmac_stress_all.84344622958294106127967401935823569470298054029206808599063135945281850226426
Line 1239, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_stress_all/latest/run.log

  UVM_FATAL @ 18030463546 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (43 [0x2b] vs 228 [0xe4]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 18030463546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 3 failures.

15.kmac_entropy_refresh.5453885796076463214446062318044205557471156676568651922863756597755319997557
Line 353, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/15.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 6503871799 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (25 [0x19] vs 213 [0xd5]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 6503871799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

34.kmac_entropy_refresh.94073393280922775233641793005970015094969706021249025103689232374236535018030
Line 325, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/34.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 2638943524 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (239 [0xef] vs 175 [0xaf]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 2638943524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test kmac_app has 1 failures.

29.kmac_app.8152373938492976152067095380536728642590566072008082777723980430928500512526
Line 481, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/29.kmac_app/latest/run.log

  UVM_FATAL @ 7651012566 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (2 [0x2] vs 243 [0xf3]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 7651012566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
- Test kmac_app has 1 failures.
  - 1.kmac_app.46461099265155418023926162107666393069764913330162383879267083213491059541722
    Line 932, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_app/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_entropy_refresh has 1 failures.
  - 4.kmac_entropy_refresh.68239993157060887802731819914498452262715060675224095899587950404489800483117
    Line 736, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_entropy_refresh/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_error has 1 failures.
  - 6.kmac_error.112407636622441535996085519726172189979670505021178242558323071167890897206029
    Line 1108, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_error/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_burst_write has 1 failures.
  - 38.kmac_burst_write.104984345549112542601528741927163525981677183723329492347528254922194625572671
    Line 681, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/38.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 4 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 3.kmac_stress_all_with_rand_reset.111267906476231720796992064871201423337781546521580350185192422974192295760961
    Line 1541, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 62626672058 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 62626672058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_stress_all has 2 failures.
  - 23.kmac_stress_all.33363191079753151722717620220881852750789641108545759388836169326629733132306
    Line 1678, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/23.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 165859395015 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 165859395015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 27.kmac_stress_all.32788195434528336366619521429502333165196451211569407143300127639387729832127
    Line 611, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/27.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 25427263287 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 25427263287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_error has 1 failures.
  - 29.kmac_error.25286907283898268571440556322184539904727721243398845765665458299639756674808
    Line 744, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/29.kmac_error/latest/run.log
```
  UVM_FATAL @ 10045660658 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 10045660658 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 4 failures:
- Test kmac_test_vectors_kmac has 1 failures.
  - 4.kmac_test_vectors_kmac.108690829451616220207167333651670440855874973625982880524141910525705404198296
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_test_vectors_kmac/latest/run.log
```
  UVM_ERROR @  61975640 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  61975640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_shake_256 has 1 failures.
  - 19.kmac_test_vectors_shake_256.115188484354457728456278714746040243727917491166347089105563962789483081418781
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_test_vectors_shake_256/latest/run.log
```
  UVM_ERROR @  71000071 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  71000071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_kmac_xof has 1 failures.
  - 31.kmac_test_vectors_kmac_xof.113618738437070586491467773742844167838265211229774529109710049542770445760196
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/31.kmac_test_vectors_kmac_xof/latest/run.log
```
  UVM_ERROR @  59726261 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  59726261 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_sha3_224 has 1 failures.
  - 32.kmac_test_vectors_sha3_224.108390366679756434172082054028396166381353434732480075624090195755090733690034
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/32.kmac_test_vectors_sha3_224/latest/run.log
```
  UVM_ERROR @  33581002 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  33581002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job kmac_masked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:
- Test kmac_long_msg_and_output has 1 failures.
  - 2.kmac_long_msg_and_output.30745483857827089478877901734284140421270403284508281890054342635823426170660
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:34c2cc4e-5bd2-40e1-a54b-0c9e4af2d96d
```
- Test kmac_test_vectors_shake_128 has 1 failures.
  - 3.kmac_test_vectors_shake_128.53090786278018131940190078451248565058723032823353501809521408217758894432061
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_test_vectors_shake_128/latest/run.log
```
  Job ID: smart:b84f4b90-a6c3-4ec7-8fcd-9137a5da50ad
```