KMAC/MASKED Simulation Results

Thursday June 27 2024 23:02:31 UTC

GitHub Revision: `8db2a18db1`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 100513533386727882033709335126269317053614297947080434367729937568368619502352

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.555m	16.472ms	49	50	98.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.190s	87.362us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.340s	35.217us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	17.850s	4.185ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.640s	1.504ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.580s	33.850us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.340s	35.217us	20	20	100.00
		kmac_csr_aliasing	9.640s	1.504ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.780s	11.406us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.480s	76.394us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	long_msg_and_output	kmac_long_msg_and_output	55.239m	1.248s	50	50	100.00
V2	burst_write	kmac_burst_write	25.725m	15.990ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	41.237m	101.915ms	48	50	96.00
		kmac_test_vectors_sha3_256	39.637m	615.844ms	48	50	96.00
		kmac_test_vectors_sha3_384	34.102m	1.010s	50	50	100.00
		kmac_test_vectors_sha3_512	24.754m	294.790ms	50	50	100.00
		kmac_test_vectors_shake_128	1.779h	1.067s	50	50	100.00
		kmac_test_vectors_shake_256	1.724h	2.170s	50	50	100.00
		kmac_test_vectors_kmac	7.020s	608.978us	50	50	100.00
		kmac_test_vectors_kmac_xof	7.150s	3.128ms	50	50	100.00
V2	sideload	kmac_sideload	9.177m	21.967ms	50	50	100.00
V2	app	kmac_app	6.546m	18.600ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.852m	84.051ms	9	10	90.00
V2	entropy_refresh	kmac_entropy_refresh	7.082m	37.293ms	47	50	94.00
V2	error	kmac_error	8.394m	29.942ms	50	50	100.00
V2	key_error	kmac_key_error	15.960s	9.205ms	49	50	98.00
V2	edn_timeout_error	kmac_edn_timeout_error	51.280s	697.080us	19	20	95.00
V2	entropy_mode_error	kmac_entropy_mode_error	50.200s	9.727ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.372m	16.896ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	56.620s	4.586ms	50	50	100.00
V2	stress_all	kmac_stress_all	41.694m	182.994ms	48	50	96.00
V2	intr_test	kmac_intr_test	0.890s	23.726us	50	50	100.00
V2	alert_test	kmac_alert_test	0.910s	24.321us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.340s	141.683us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.340s	141.683us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.190s	87.362us	5	5	100.00
		kmac_csr_rw	1.340s	35.217us	20	20	100.00
		kmac_csr_aliasing	9.640s	1.504ms	5	5	100.00
		kmac_same_csr_outstanding	2.750s	240.391us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.190s	87.362us	5	5	100.00
		kmac_csr_rw	1.340s	35.217us	20	20	100.00
		kmac_csr_aliasing	9.640s	1.504ms	5	5	100.00
		kmac_same_csr_outstanding	2.750s	240.391us	20	20	100.00
V2		TOTAL			1036	1050	98.67
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.530s	72.896us	19	20	95.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.530s	72.896us	19	20	95.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.530s	72.896us	19	20	95.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.530s	72.896us	19	20	95.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.140s	130.396us	16	20	80.00
V2S	tl_intg_err	kmac_sec_cm	1.669m	28.453ms	5	5	100.00
		kmac_tl_intg_err	5.320s	250.210us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.320s	250.210us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	56.620s	4.586ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.555m	16.472ms	49	50	98.00
V2S	sec_cm_key_sideload	kmac_sideload	9.177m	21.967ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.530s	72.896us	19	20	95.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.669m	28.453ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.669m	28.453ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.669m	28.453ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.555m	16.472ms	49	50	98.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	56.620s	4.586ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.669m	28.453ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.178m	13.315ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.555m	16.472ms	49	50	98.00
V2S		TOTAL			70	75	93.33
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	30.520m	42.880ms	3	10	30.00
V3		TOTAL			3	10	30.00
		TOTAL			1223	1250	97.84

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	25	25	16	64.00
V2S	5	5	3	60.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.40	97.89	92.55	99.89	78.17	95.53	98.89	97.88

Failure Buckets

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 5 failures:

Test kmac_app_with_partial_data has 1 failures.

1.kmac_app_with_partial_data.76658428006912045004043808808728108940655731047664242492781349194875629783678
Line 881, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_app_with_partial_data/latest/run.log

  UVM_FATAL @ 24329675526 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (0 [0x0] vs 72 [0x48]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 24329675526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app has 1 failures.

12.kmac_app.20945374763284423544712241430275160183046157390777422033939790023244132292514
Line 421, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/12.kmac_app/latest/run.log

  UVM_FATAL @ 45754475915 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (197 [0xc5] vs 9 [0x9]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 45754475915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 1 failures.

12.kmac_stress_all.18906930932098897158832902467320986159562626717360229368352477090952023790074
Line 935, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/12.kmac_stress_all/latest/run.log

  UVM_FATAL @ 202014042412 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (101 [0x65] vs 73 [0x49]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 202014042412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 2 failures.

24.kmac_entropy_refresh.26662346129102372948090644090269305559309696471047326474846506788523251592624
Line 285, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/24.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 2845853671 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (15 [0xf] vs 98 [0x62]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 2845853671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

30.kmac_entropy_refresh.1622211129252621332240810945520929312738968184485413128951671450056039347052
Line 465, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/30.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 23070753222 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (92 [0x5c] vs 134 [0x86]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 23070753222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: * Check_csr_read_clear_staged_val task: check update_err status has 5 failures:

Test kmac_shadow_reg_errors_with_csr_rw has 4 failures.

7.kmac_shadow_reg_errors_with_csr_rw.73685112173160882775865223543448248883414598863419016221257004044509851012994
Line 255, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  44865490 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  44865490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

10.kmac_shadow_reg_errors_with_csr_rw.99095116980801112452803234277525710266857425556289739902171907206077884687248
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/10.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @   8886580 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @   8886580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test kmac_shadow_reg_errors has 1 failures.

12.kmac_shadow_reg_errors.97692153612314030895687693920386825433018068432997255761454833387620755923342
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/12.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @   5714411 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @   5714411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:828) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 4 failures:
- Test kmac_stress_all_with_rand_reset has 4 failures.
  - 3.kmac_stress_all_with_rand_reset.87278351525792011986108528303977211544614768708691569037893457090518248766847
    Line 788, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 173753949699 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 173753949699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.kmac_stress_all_with_rand_reset.44774248886741714007643437094784815793801176842969021839016714236724844982529
    Line 678, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 108387366085 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 108387366085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 3 failures:

Test kmac_test_vectors_sha3_256 has 1 failures.

0.kmac_test_vectors_sha3_256.86871713738401615295081019143595584810288109336104011260141484082648896426646
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_256/latest/run.log

  [make]: simulate
  cd /workspace/0.kmac_test_vectors_sha3_256/latest && /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821744278 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_256.821744278 +enable_masking=1 +sw_key_masked=0
  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Jun 27 19:28 2024
  Cannot find license file.
  Make sure that you have a license file and that your
  LM_LICENSE_FILE is pointing to the right location.
  
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:187: simulate] Error 255

Test kmac_edn_timeout_error has 1 failures.

4.kmac_edn_timeout_error.62490983410561103175834557299666585875044782550456860398143692450083120284033
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_edn_timeout_error/latest/run.log

  [make]: simulate
  cd /workspace/4.kmac_edn_timeout_error/latest && /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333357953 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_edn_timeout_error.3333357953 +enable_masking=1 +sw_key_masked=0
  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Jun 27 19:28 2024
  Cannot find license file.
  Make sure that you have a license file and that your
  LM_LICENSE_FILE is pointing to the right location.
  
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:187: simulate] Error 255

Test kmac_smoke has 1 failures.

5.kmac_smoke.14434711712652701456716855500252572219544260129465165768161744887953648060840
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_smoke/latest/run.log

  [make]: simulate
  cd /workspace/5.kmac_smoke/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166870952 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_smoke.1166870952 +enable_masking=1 +sw_key_masked=0
  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Jun 27 19:28 2024
  Cannot find license file.
  Make sure that you have a license file and that your
  LM_LICENSE_FILE is pointing to the right location.
  
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:187: simulate] Error 255

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 3 failures:
- Test kmac_stress_all has 1 failures.
  - 11.kmac_stress_all.94239223605181057333920873453403929461165884559128897665446724041625550238985
    Line 624, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_stress_all/latest/run.log
```
  UVM_ERROR @ 11113164151 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 11113164151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_sha3_224 has 1 failures.
  - 24.kmac_test_vectors_sha3_224.91373315498397703017468222603487281658095943495254519759994368314270221706880
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/24.kmac_test_vectors_sha3_224/latest/run.log
```
  UVM_ERROR @  74389218 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  74389218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_sha3_256 has 1 failures.
  - 34.kmac_test_vectors_sha3_256.32266147535000905599161167381086549567011262916116946275158172877975940273652
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/34.kmac_test_vectors_sha3_256/latest/run.log
```
  UVM_ERROR @  18983726 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  18983726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 2 failures:
- Test kmac_stress_all_with_rand_reset has 2 failures.
  - 0.kmac_stress_all_with_rand_reset.4968674318274042535246165990442838633375591793157978431886419739045653212375
    Line 1363, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 15424080605 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483680 [0x80000020]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 15424080605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.kmac_stress_all_with_rand_reset.98306809158147275476293976148427501803289066907835590102820534736023162449714
    Line 2660, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 42879696192 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483648 [0x80000000]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 42879696192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job kmac_masked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 2.kmac_stress_all_with_rand_reset.18709045281874417094993896869851911102257320400045428308478340695481528587869
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:80d2fde0-11c5-4057-b9d4-d446d96be558
```
- Test kmac_test_vectors_sha3_224 has 1 failures.
  - 3.kmac_test_vectors_sha3_224.27513273004652615548378083609528458843039781824631970269166267951806031943086
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_224/latest/run.log
```
  Job ID: smart:30715f03-e286-4ace-a93e-4d8413e5b9d1
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test kmac_entropy_refresh has 1 failures.
  - 15.kmac_entropy_refresh.30347024150856768469574208795342650056964986368184262460970698786525088226851
    Line 1116, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/15.kmac_entropy_refresh/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_burst_write has 1 failures.
  - 48.kmac_burst_write.8560468442529042420410751347227469753218689571401893298703363605922734835247
    Line 994, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/48.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (kmac_base_vseq.sv:382) [kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == *) intr_pins[KmacErr] is not set! has 1 failures:
- Test kmac_key_error has 1 failures.
  - 18.kmac_key_error.61256623076990019520060089763927428242115794833345192188439671047404858450897
    Line 275, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/18.kmac_key_error/latest/run.log
```
  UVM_ERROR @ 807832541 ps: (kmac_base_vseq.sv:382) [uvm_test_top.env.virtual_sequencer.kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == 1) intr_pins[KmacErr] is not set!
  UVM_INFO @ 807832541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```