3d5220a43f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | kmac_smoke | 1.481m | 17.062ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | kmac_csr_hw_reset | 1.220s | 56.587us | 5 | 5 | 100.00 |
| V1 | csr_rw | kmac_csr_rw | 1.240s | 116.141us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | kmac_csr_bit_bash | 18.380s | 1.029ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | kmac_csr_aliasing | 11.080s | 3.219ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | kmac_csr_mem_rw_with_rand_reset | 2.660s | 123.630us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | kmac_csr_rw | 1.240s | 116.141us | 20 | 20 | 100.00 |
| kmac_csr_aliasing | 11.080s | 3.219ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | kmac_mem_walk | 0.790s | 13.747us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | kmac_mem_partial_access | 1.630s | 39.700us | 5 | 5 | 100.00 |
| V1 | TOTAL | 115 | 115 | 100.00 | |||
| V2 | long_msg_and_output | kmac_long_msg_and_output | 56.999m | 92.015ms | 48 | 50 | 96.00 |
| V2 | burst_write | kmac_burst_write | 27.411m | 30.607ms | 50 | 50 | 100.00 |
| V2 | test_vectors | kmac_test_vectors_sha3_224 | 43.609m | 1.423s | 49 | 50 | 98.00 |
| kmac_test_vectors_sha3_256 | 40.235m | 1.010s | 48 | 50 | 96.00 | ||
| kmac_test_vectors_sha3_384 | 30.740m | 232.378ms | 49 | 50 | 98.00 | ||
| kmac_test_vectors_sha3_512 | 21.513m | 148.370ms | 49 | 50 | 98.00 | ||
| kmac_test_vectors_shake_128 | 1.836h | 1.224s | 50 | 50 | 100.00 | ||
| kmac_test_vectors_shake_256 | 1.591h | 1.443s | 50 | 50 | 100.00 | ||
| kmac_test_vectors_kmac | 7.270s | 1.505ms | 49 | 50 | 98.00 | ||
| kmac_test_vectors_kmac_xof | 7.490s | 439.165us | 50 | 50 | 100.00 | ||
| V2 | sideload | kmac_sideload | 9.131m | 22.964ms | 50 | 50 | 100.00 |
| V2 | app | kmac_app | 7.395m | 50.095ms | 48 | 50 | 96.00 |
| V2 | app_with_partial_data | kmac_app_with_partial_data | 7.841m | 83.017ms | 9 | 10 | 90.00 |
| V2 | entropy_refresh | kmac_entropy_refresh | 7.951m | 86.722ms | 49 | 50 | 98.00 |
| V2 | error | kmac_error | 9.166m | 103.908ms | 47 | 50 | 94.00 |
| V2 | key_error | kmac_key_error | 13.170s | 5.761ms | 50 | 50 | 100.00 |
| V2 | edn_timeout_error | kmac_edn_timeout_error | 56.960s | 6.361ms | 20 | 20 | 100.00 |
| V2 | entropy_mode_error | kmac_entropy_mode_error | 41.900s | 4.226ms | 20 | 20 | 100.00 |
| V2 | entropy_ready_error | kmac_entropy_ready_error | 1.137m | 25.166ms | 10 | 10 | 100.00 |
| V2 | lc_escalation | kmac_lc_escalation | 51.590s | 2.886ms | 50 | 50 | 100.00 |
| V2 | stress_all | kmac_stress_all | 54.668m | 211.603ms | 47 | 50 | 94.00 |
| V2 | intr_test | kmac_intr_test | 0.920s | 16.425us | 50 | 50 | 100.00 |
| V2 | alert_test | kmac_alert_test | 0.920s | 67.904us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | kmac_tl_errors | 3.600s | 399.063us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | kmac_tl_errors | 3.600s | 399.063us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | kmac_csr_hw_reset | 1.220s | 56.587us | 5 | 5 | 100.00 |
| kmac_csr_rw | 1.240s | 116.141us | 20 | 20 | 100.00 | ||
| kmac_csr_aliasing | 11.080s | 3.219ms | 5 | 5 | 100.00 | ||
| kmac_same_csr_outstanding | 2.940s | 647.811us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | kmac_csr_hw_reset | 1.220s | 56.587us | 5 | 5 | 100.00 |
| kmac_csr_rw | 1.240s | 116.141us | 20 | 20 | 100.00 | ||
| kmac_csr_aliasing | 11.080s | 3.219ms | 5 | 5 | 100.00 | ||
| kmac_same_csr_outstanding | 2.940s | 647.811us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1032 | 1050 | 98.29 | |||
| V2S | shadow_reg_update_error | kmac_shadow_reg_errors | 1.500s | 493.636us | 19 | 20 | 95.00 |
| V2S | shadow_reg_read_clear_staged_value | kmac_shadow_reg_errors | 1.500s | 493.636us | 19 | 20 | 95.00 |
| V2S | shadow_reg_storage_error | kmac_shadow_reg_errors | 1.500s | 493.636us | 19 | 20 | 95.00 |
| V2S | shadowed_reset_glitch | kmac_shadow_reg_errors | 1.500s | 493.636us | 19 | 20 | 95.00 |
| V2S | shadow_reg_update_error_with_csr_rw | kmac_shadow_reg_errors_with_csr_rw | 2.750s | 395.678us | 18 | 20 | 90.00 |
| V2S | tl_intg_err | kmac_sec_cm | 2.219m | 133.636ms | 5 | 5 | 100.00 |
| kmac_tl_intg_err | 5.330s | 756.475us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | kmac_tl_intg_err | 5.330s | 756.475us | 20 | 20 | 100.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | kmac_lc_escalation | 51.590s | 2.886ms | 50 | 50 | 100.00 |
| V2S | sec_cm_sw_key_key_masking | kmac_smoke | 1.481m | 17.062ms | 50 | 50 | 100.00 |
| V2S | sec_cm_key_sideload | kmac_sideload | 9.131m | 22.964ms | 50 | 50 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_shadow | kmac_shadow_reg_errors | 1.500s | 493.636us | 19 | 20 | 95.00 |
| V2S | sec_cm_fsm_sparse | kmac_sec_cm | 2.219m | 133.636ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ctr_redun | kmac_sec_cm | 2.219m | 133.636ms | 5 | 5 | 100.00 |
| V2S | sec_cm_packer_ctr_redun | kmac_sec_cm | 2.219m | 133.636ms | 5 | 5 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_regwen | kmac_smoke | 1.481m | 17.062ms | 50 | 50 | 100.00 |
| V2S | sec_cm_fsm_global_esc | kmac_lc_escalation | 51.590s | 2.886ms | 50 | 50 | 100.00 |
| V2S | sec_cm_fsm_local_esc | kmac_sec_cm | 2.219m | 133.636ms | 5 | 5 | 100.00 |
| V2S | sec_cm_absorbed_ctrl_mubi | kmac_mubi | 5.682m | 11.906ms | 9 | 10 | 90.00 |
| V2S | sec_cm_sw_cmd_ctrl_sparse | kmac_smoke | 1.481m | 17.062ms | 50 | 50 | 100.00 |
| V2S | TOTAL | 71 | 75 | 94.67 | |||
| V3 | throughput | kmac_throughput | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | kmac_stress_all_with_rand_reset | 47.136m | 95.052ms | 3 | 10 | 30.00 |
| V3 | TOTAL | 3 | 10 | 30.00 | |||
| TOTAL | 1221 | 1250 | 97.68 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 8 | 100.00 |
| V2 | 25 | 25 | 14 | 56.00 |
| V2S | 5 | 5 | 2 | 40.00 |
| V3 | 2 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 94.11 | 97.89 | 92.62 | 99.89 | 76.06 | 95.53 | 98.89 | 97.88 |
UVM_ERROR (cip_base_vseq.sv:828) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 7 failures:
0.kmac_stress_all_with_rand_reset.84696665192958820051747037327520118665251710270235567403767583157891929286191
Line 646, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 13250340307 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 13250340307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.kmac_stress_all_with_rand_reset.10465859599157419217847275083016022914646711779307703539786188955452833231865
Line 866, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 9527603002 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 9527603002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 5 failures:
Test kmac_mubi has 1 failures.
5.kmac_mubi.101154108919085884806031846001629330155317291565830449133613975031993522406701
Line 483, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_mubi/latest/run.log
UVM_FATAL @ 8661386591 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (17 [0x11] vs 179 [0xb3]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 8661386591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_stress_all has 2 failures.
11.kmac_stress_all.41389955116711893284176678030099366327539052270864600638202587888327816853749
Line 1229, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_stress_all/latest/run.log
UVM_FATAL @ 68023945848 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (233 [0xe9] vs 176 [0xb0]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 68023945848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
41.kmac_stress_all.51318778163950243846576097750315032702916999364721484552564576266979194139921
Line 595, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/41.kmac_stress_all/latest/run.log
UVM_FATAL @ 49654517735 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (86 [0x56] vs 119 [0x77]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 49654517735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_entropy_refresh has 1 failures.
14.kmac_entropy_refresh.83394982216468822280017752689887211625145771182907534083158192163470122401459
Line 763, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_entropy_refresh/latest/run.log
UVM_FATAL @ 74410812473 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (91 [0x5b] vs 66 [0x42]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 74410812473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_app has 1 failures.
39.kmac_app.3306191257411036507263238216458569627546746292134522867068859270850242580502
Line 459, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/39.kmac_app/latest/run.log
UVM_FATAL @ 3351289372 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (248 [0xf8] vs 253 [0xfd]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 3351289372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed Job returned non-zero exit code has 5 failures:
Test kmac_long_msg_and_output has 2 failures.
10.kmac_long_msg_and_output.53900922176761447237344887476689498723489988514795030445846798669435127560711
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/10.kmac_long_msg_and_output/latest/run.log
[make]: simulate
cd /workspace/10.kmac_long_msg_and_output/latest && /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757065223 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_long_msg_and_output.2757065223 +enable_masking=1 +sw_key_masked=0
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jun 28 18:40 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:187: simulate] Error 255
15.kmac_long_msg_and_output.79790692847374263295051551042803241330797171816872015514565717969946851319598
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/15.kmac_long_msg_and_output/latest/run.log
[make]: simulate
cd /workspace/15.kmac_long_msg_and_output/latest && /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117667630 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_long_msg_and_output.4117667630 +enable_masking=1 +sw_key_masked=0
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jun 28 18:45 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:187: simulate] Error 255
Test kmac_test_vectors_sha3_384 has 1 failures.
13.kmac_test_vectors_sha3_384.11083947226695241646514736794725548343009872052574222972757125958982255342111
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/13.kmac_test_vectors_sha3_384/latest/run.log
[make]: simulate
cd /workspace/13.kmac_test_vectors_sha3_384/latest && /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190990879 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_384.4190990879 +enable_masking=1 +sw_key_masked=0
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jun 28 18:43 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:187: simulate] Error 255
Test kmac_test_vectors_sha3_256 has 1 failures.
14.kmac_test_vectors_sha3_256.51811739726956822501561907132081452319876500498551942513504898475451919949687
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_test_vectors_sha3_256/latest/run.log
[make]: simulate
cd /workspace/14.kmac_test_vectors_sha3_256/latest && /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097026423 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_256.3097026423 +enable_masking=1 +sw_key_masked=0
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jun 28 18:44 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:187: simulate] Error 255
Test kmac_app has 1 failures.
16.kmac_app.75079470434142450044977215605024592579422422335594975164061770771093937098032
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/16.kmac_app/latest/run.log
[make]: simulate
cd /workspace/16.kmac_app/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845216048 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_app.2845216048 +enable_masking=1 +sw_key_masked=0
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jun 28 18:47 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:187: simulate] Error 255
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 4 failures:
Test kmac_test_vectors_sha3_512 has 1 failures.
0.kmac_test_vectors_sha3_512.112988519036085540488392818456197587379745806012931004926277571529194933266249
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_512/latest/run.log
UVM_ERROR @ 143074550 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 143074550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_test_vectors_sha3_224 has 1 failures.
25.kmac_test_vectors_sha3_224.77389800366775777006327160271061511045452164863247467447958446241759450523851
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/25.kmac_test_vectors_sha3_224/latest/run.log
UVM_ERROR @ 34926121 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 34926121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_test_vectors_kmac has 1 failures.
29.kmac_test_vectors_kmac.6443593966326394206345283464163750128098966290863975259547295613591604982441
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/29.kmac_test_vectors_kmac/latest/run.log
UVM_ERROR @ 38145757 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 38145757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_test_vectors_sha3_256 has 1 failures.
45.kmac_test_vectors_sha3_256.93740492200611005800327160912888472236618620062163482045153303306845340704981
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/45.kmac_test_vectors_sha3_256/latest/run.log
UVM_ERROR @ 73702407 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 73702407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: * Check_csr_read_clear_staged_val task: check update_err status has 3 failures:
Test kmac_shadow_reg_errors_with_csr_rw has 2 failures.
5.kmac_shadow_reg_errors_with_csr_rw.44721870566809748786226423718546693399580400001573724648118947017740072870528
Line 255, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
UVM_ERROR @ 106261562 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0 Check_csr_read_clear_staged_val task: check update_err status
UVM_INFO @ 106261562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
19.kmac_shadow_reg_errors_with_csr_rw.45542377496822882685065528131832250727794498592409234523278552707606868167514
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
UVM_ERROR @ 41551264 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0 Check_csr_read_clear_staged_val task: check update_err status
UVM_INFO @ 41551264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_shadow_reg_errors has 1 failures.
14.kmac_shadow_reg_errors.101271496610257667574889304648549347279887079020121019035010126364759762785569
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_shadow_reg_errors/latest/run.log
UVM_ERROR @ 2850031 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0 Check_csr_read_clear_staged_val task: check update_err status
UVM_INFO @ 2850031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 3 failures:
Test kmac_error has 2 failures.
18.kmac_error.99714243592087164602647951254011180562243861641803871135388166891081304591488
Line 759, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/18.kmac_error/latest/run.log
UVM_FATAL @ 10142863173 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
UVM_INFO @ 10142863173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
30.kmac_error.83423583920416002423776937035072436454640883983194007634098304029476436994284
Line 312, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/30.kmac_error/latest/run.log
UVM_FATAL @ 10150782759 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
UVM_INFO @ 10150782759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_stress_all has 1 failures.
26.kmac_stress_all.101905204553396352215925467031613775424623938164488880482920711066658786631356
Line 1440, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/26.kmac_stress_all/latest/run.log
UVM_FATAL @ 184227097170 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
UVM_INFO @ 184227097170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
Test kmac_app_with_partial_data has 1 failures.
7.kmac_app_with_partial_data.71089998756977131226998889750825047256974727563164760490456226466261933184434
Line 998, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_app_with_partial_data/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_error has 1 failures.
26.kmac_error.24850403281527453179155851966120146816399515367965191341680472224329055439836
Line 898, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/26.kmac_error/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---