KMAC/MASKED Simulation Results

Saturday June 29 2024 23:02:35 UTC

GitHub Revision: `b33f0bcb4a`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 9407974028806500767465982655187958599819354731549473124644158596869486113221

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.438m	15.794ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.140s	29.169us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.290s	320.387us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	21.020s	2.880ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.870s	769.269us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.550s	238.734us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.290s	320.387us	20	20	100.00
		kmac_csr_aliasing	9.870s	769.269us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.790s	15.748us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.540s	37.601us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	53.255m	264.917ms	50	50	100.00
V2	burst_write	kmac_burst_write	26.316m	18.597ms	46	50	92.00
V2	test_vectors	kmac_test_vectors_sha3_224	42.913m	566.173ms	50	50	100.00
		kmac_test_vectors_sha3_256	40.698m	159.400ms	50	50	100.00
		kmac_test_vectors_sha3_384	33.129m	240.483ms	50	50	100.00
		kmac_test_vectors_sha3_512	25.699m	205.070ms	50	50	100.00
		kmac_test_vectors_shake_128	1.994h	3.210s	50	50	100.00
		kmac_test_vectors_shake_256	1.618h	843.709ms	49	50	98.00
		kmac_test_vectors_kmac	7.290s	779.808us	50	50	100.00
		kmac_test_vectors_kmac_xof	7.340s	1.262ms	50	50	100.00
V2	sideload	kmac_sideload	10.600m	74.633ms	50	50	100.00
V2	app	kmac_app	7.024m	71.131ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.587m	12.336ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	7.283m	13.583ms	49	50	98.00
V2	error	kmac_error	8.569m	44.236ms	50	50	100.00
V2	key_error	kmac_key_error	14.580s	3.955ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	55.170s	4.632ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	40.840s	506.260us	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	59.110s	5.937ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	1.021m	1.043ms	50	50	100.00
V2	stress_all	kmac_stress_all	1.006h	200.419ms	47	50	94.00
V2	intr_test	kmac_intr_test	0.940s	14.092us	50	50	100.00
V2	alert_test	kmac_alert_test	0.930s	235.111us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.610s	457.525us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.610s	457.525us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.140s	29.169us	5	5	100.00
		kmac_csr_rw	1.290s	320.387us	20	20	100.00
		kmac_csr_aliasing	9.870s	769.269us	5	5	100.00
		kmac_same_csr_outstanding	2.590s	106.539us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.140s	29.169us	5	5	100.00
		kmac_csr_rw	1.290s	320.387us	20	20	100.00
		kmac_csr_aliasing	9.870s	769.269us	5	5	100.00
		kmac_same_csr_outstanding	2.590s	106.539us	20	20	100.00
V2		TOTAL			1041	1050	99.14
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.460s	51.119us	15	20	75.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.460s	51.119us	15	20	75.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.460s	51.119us	15	20	75.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.460s	51.119us	15	20	75.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.020s	123.426us	19	20	95.00
V2S	tl_intg_err	kmac_sec_cm	1.744m	9.158ms	5	5	100.00
		kmac_tl_intg_err	6.040s	2.556ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	6.040s	2.556ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.021m	1.043ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.438m	15.794ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	10.600m	74.633ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.460s	51.119us	15	20	75.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.744m	9.158ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.744m	9.158ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.744m	9.158ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.438m	15.794ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.021m	1.043ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.744m	9.158ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.840m	16.731ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.438m	15.794ms	50	50	100.00
V2S		TOTAL			69	75	92.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	26.577m	60.422ms	1	10	10.00
V3		TOTAL			1	10	10.00
		TOTAL			1226	1250	98.08

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	21	84.00
V2S	5	5	3	60.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.20	97.89	92.58	99.89	76.76	95.53	98.89	97.88

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 6 failures:
- Test kmac_stress_all_with_rand_reset has 6 failures.
  - 0.kmac_stress_all_with_rand_reset.87538882470063303451893463344222511998663686463081546312982700223864152174646
    Line 877, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 36909982336 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 36909982336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.111965210640878686032627121563097239708118318282927034342312953108380848654609
    Line 821, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 17949663435 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 17949663435 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: * Check_csr_read_clear_staged_val task: check update_err status has 6 failures:

Test kmac_shadow_reg_errors has 5 failures.

1.kmac_shadow_reg_errors.7416432883067415782706508051439184700277601351530625006264897726410940591943
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @  15011058 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  15011058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.kmac_shadow_reg_errors.34780596517725213710782031859641578526921288564447384053856929664970485477191
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @  21879388 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  21879388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

1.kmac_shadow_reg_errors_with_csr_rw.70376495559069373483886704907235939858329138214784895184794836741219848347007
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  55830744 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  55830744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
- Test kmac_burst_write has 4 failures.
  - 15.kmac_burst_write.1738472824064268061318988861952843882148627620239145588509026384077559143246
    Line 746, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/15.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 27.kmac_burst_write.94472962305799236969892679330777280378817503831512180561006415485493702577251
    Line 878, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/27.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 3 failures:
- Test kmac_stress_all_with_rand_reset has 3 failures.
  - 4.kmac_stress_all_with_rand_reset.1204759734605582186775939067206876205672062676514432883814033530119931285129
    Line 766, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 100011524551 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483752 [0x80000068]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 100011524551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.kmac_stress_all_with_rand_reset.101613251139384664906919695452558734676708678026133144069688265279247340378983
    Line 730, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 13182892732 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483744 [0x80000060]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 13182892732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 2 failures:
- Test kmac_stress_all has 2 failures.
  - 23.kmac_stress_all.30018213483449090156065446354097196693027011919120935754320512255539279965585
    Line 1753, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/23.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 245793205804 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 245793205804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 34.kmac_stress_all.21733532000755617152359313407227633236647100230396761544425004933952598219067
    Line 1336, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/34.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 29450447528 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 29450447528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 2 failures:
- Test kmac_stress_all has 1 failures.
  - 27.kmac_stress_all.114607942726162165416816503000089709223641150690507567885348492599613740998036
    Line 629, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/27.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 7351454852 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (69 [0x45] vs 95 [0x5f]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 7351454852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_entropy_refresh has 1 failures.
  - 36.kmac_entropy_refresh.95024424917661149841387304145272240373352914494042596367377147286702731518732
    Line 593, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/36.kmac_entropy_refresh/latest/run.log
```
  UVM_FATAL @ 17563500558 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (3 [0x3] vs 222 [0xde]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 17563500558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 1 failures:
- Test kmac_test_vectors_shake_256 has 1 failures.
  - 26.kmac_test_vectors_shake_256.106536868110811011198005581428664824110516339003004248467793342550350209923313
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/26.kmac_test_vectors_shake_256/latest/run.log
```
  UVM_ERROR @  43141030 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  43141030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```