KMAC/MASKED Simulation Results

Sunday June 30 2024 23:02:20 UTC

GitHub Revision: `b33f0bcb4a`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 105302396297609026156504164956156290718642058150905320202190590799028860124396

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.784m	19.336ms	49	50	98.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.120s	33.553us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.210s	95.567us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	22.660s	6.017ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	11.550s	5.352ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.750s	347.992us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.210s	95.567us	20	20	100.00
		kmac_csr_aliasing	11.550s	5.352ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.780s	89.697us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.490s	65.812us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	long_msg_and_output	kmac_long_msg_and_output	59.494m	1.053s	48	50	96.00
V2	burst_write	kmac_burst_write	25.944m	32.104ms	47	50	94.00
V2	test_vectors	kmac_test_vectors_sha3_224	47.670m	1.333s	50	50	100.00
		kmac_test_vectors_sha3_256	40.867m	730.519ms	50	50	100.00
		kmac_test_vectors_sha3_384	33.561m	391.857ms	48	50	96.00
		kmac_test_vectors_sha3_512	27.058m	705.534ms	48	50	96.00
		kmac_test_vectors_shake_128	1.873h	1.721s	50	50	100.00
		kmac_test_vectors_shake_256	1.693h	1.474s	49	50	98.00
		kmac_test_vectors_kmac	7.530s	279.972us	50	50	100.00
		kmac_test_vectors_kmac_xof	7.250s	705.917us	50	50	100.00
V2	sideload	kmac_sideload	8.616m	60.460ms	50	50	100.00
V2	app	kmac_app	7.728m	90.422ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.323m	37.980ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	8.024m	185.468ms	48	50	96.00
V2	error	kmac_error	9.106m	22.174ms	48	50	96.00
V2	key_error	kmac_key_error	14.090s	16.987ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	45.230s	36.488ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	34.410s	2.865ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.044m	6.131ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	43.190s	613.439us	50	50	100.00
V2	stress_all	kmac_stress_all	53.788m	32.875ms	48	50	96.00
V2	intr_test	kmac_intr_test	0.880s	14.964us	50	50	100.00
V2	alert_test	kmac_alert_test	0.930s	210.074us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.150s	122.166us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.150s	122.166us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.120s	33.553us	5	5	100.00
		kmac_csr_rw	1.210s	95.567us	20	20	100.00
		kmac_csr_aliasing	11.550s	5.352ms	5	5	100.00
		kmac_same_csr_outstanding	2.880s	562.652us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.120s	33.553us	5	5	100.00
		kmac_csr_rw	1.210s	95.567us	20	20	100.00
		kmac_csr_aliasing	11.550s	5.352ms	5	5	100.00
		kmac_same_csr_outstanding	2.880s	562.652us	20	20	100.00
V2		TOTAL			1033	1050	98.38
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.630s	55.677us	18	20	90.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.630s	55.677us	18	20	90.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.630s	55.677us	18	20	90.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.630s	55.677us	18	20	90.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.660s	2.361ms	18	20	90.00
V2S	tl_intg_err	kmac_sec_cm	2.086m	33.025ms	5	5	100.00
		kmac_tl_intg_err	5.320s	970.448us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.320s	970.448us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	43.190s	613.439us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.784m	19.336ms	49	50	98.00
V2S	sec_cm_key_sideload	kmac_sideload	8.616m	60.460ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.630s	55.677us	18	20	90.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	2.086m	33.025ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	2.086m	33.025ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	2.086m	33.025ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.784m	19.336ms	49	50	98.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	43.190s	613.439us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	2.086m	33.025ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.300m	114.169ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.784m	19.336ms	49	50	98.00
V2S		TOTAL			71	75	94.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.105h	466.862ms	2	10	20.00
V3		TOTAL			2	10	20.00
		TOTAL			1220	1250	97.60

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	25	25	16	64.00
V2S	5	5	3	60.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.14	97.91	92.62	99.89	76.06	95.59	99.05	97.88

Failure Buckets

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 7 failures:

Test kmac_stress_all has 1 failures.

10.kmac_stress_all.63161293860589533385438629267040154787010035224440720604108757166571761871795
Line 825, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/10.kmac_stress_all/latest/run.log

  UVM_ERROR @ 12417397849 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 12417397849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_test_vectors_sha3_512 has 2 failures.

18.kmac_test_vectors_sha3_512.78080782230210210676784516635094437058538033834024655915165579559845889330779
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/18.kmac_test_vectors_sha3_512/latest/run.log

  UVM_ERROR @  49095199 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  49095199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

20.kmac_test_vectors_sha3_512.14729315633011137585178701641894615175290020346771820639399705710008958653854
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/20.kmac_test_vectors_sha3_512/latest/run.log

  UVM_ERROR @  51350974 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  51350974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_smoke has 1 failures.

22.kmac_smoke.14756442143910963149383728752840690548857790594792348550057290360223124104069
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/22.kmac_smoke/latest/run.log

  UVM_ERROR @  77797818 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  77797818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_test_vectors_sha3_384 has 2 failures.

23.kmac_test_vectors_sha3_384.104647968538054106678155968922693756600539106805447953056795268038407600896839
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/23.kmac_test_vectors_sha3_384/latest/run.log

  UVM_ERROR @  41072233 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  41072233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

36.kmac_test_vectors_sha3_384.56527621130267839520521366325833034808098875338298341386481379805831952935421
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/36.kmac_test_vectors_sha3_384/latest/run.log

  UVM_ERROR @  31717049 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  31717049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_test_vectors_shake_256 has 1 failures.

23.kmac_test_vectors_shake_256.16724185725681103092673305705134286182281930210816822814279109779707393760862
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/23.kmac_test_vectors_shake_256/latest/run.log

  UVM_ERROR @  42773876 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  42773876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:828) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 5 failures:
- Test kmac_stress_all_with_rand_reset has 5 failures.
  - 0.kmac_stress_all_with_rand_reset.92886211620698418687021470098948295561335578584583096364411394143649242809954
    Line 456, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 32339685041 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 32339685041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.kmac_stress_all_with_rand_reset.55297597198741493415681399860174238381237546815296247841626692666411037407666
    Line 785, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 23732674903 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 23732674903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 5 failures:

Test kmac_entropy_refresh has 2 failures.

3.kmac_entropy_refresh.84503122526616071302813208448320143043116641916046008580233975738446599284036
Line 613, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 6713487829 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (132 [0x84] vs 183 [0xb7]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 6713487829 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

28.kmac_entropy_refresh.14862167150743689911300302089171949045639970531466473232002488949611126005387
Line 773, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/28.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 30974459029 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (36 [0x24] vs 163 [0xa3]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 30974459029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 1 failures.

6.kmac_stress_all.7774911353667892513942391840872889322773958871586034774194096337606055966556
Line 877, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_stress_all/latest/run.log

  UVM_FATAL @ 51515330472 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (104 [0x68] vs 21 [0x15]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 51515330472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all_with_rand_reset has 1 failures.

7.kmac_stress_all_with_rand_reset.90951274889407294311535080058698762817024192808574549194252026714362325581840
Line 799, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 5094051871 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (222 [0xde] vs 220 [0xdc]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 5094051871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app has 1 failures.

23.kmac_app.10854623420254164312974179312483233335799250616379007704963091966381977901497
Line 669, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/23.kmac_app/latest/run.log

  UVM_FATAL @ 5669162482 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (13 [0xd] vs 235 [0xeb]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 5669162482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
- Test kmac_burst_write has 3 failures.
  - 4.kmac_burst_write.19685564275116532804319360646185112601162017530591023766636387108641282560734
    Line 986, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.kmac_burst_write.48139060361730674975170316835090860177979834818163407960828119597956730512595
    Line 1202, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test kmac_error has 1 failures.
  - 47.kmac_error.108410192965895655490475259594539519699983207497740737035997766637784943049863
    Line 818, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/47.kmac_error/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: * Check_csr_read_clear_staged_val task: check update_err status has 4 failures:

Test kmac_shadow_reg_errors has 2 failures.

5.kmac_shadow_reg_errors.42630082082084828065482465313642290964057962375657447588455614765226090712854
Line 255, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @  17446493 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  17446493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

18.kmac_shadow_reg_errors.4743411622696757284319916697145206529234666707367068676428895430837275378231
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/18.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @   3201737 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @   3201737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_shadow_reg_errors_with_csr_rw has 2 failures.

9.kmac_shadow_reg_errors_with_csr_rw.61364357613461777498119187451498319352511674665045552842758225932195449212813
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  52379292 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  52379292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

17.kmac_shadow_reg_errors_with_csr_rw.26826793248238238834640959678332370710615906547968410470764352472973247198170
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/17.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  44450804 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  44450804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 2 failures:
- Test kmac_stress_all_with_rand_reset has 2 failures.
  - 1.kmac_stress_all_with_rand_reset.106019865516364286067564190140053102249837220050237618999748623854570320298376
    Line 620, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9036823854 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483664 [0x80000010]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 9036823854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.kmac_stress_all_with_rand_reset.102982753422233367838974763627656309876544263477355668358056599799371177426136
    Line 667, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 110898787061 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483768 [0x80000078]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 110898787061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job kmac_masked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:
- Test kmac_long_msg_and_output has 2 failures.
  - 17.kmac_long_msg_and_output.31956520677907818265003865526354980386585158337018667462322025208116595138872
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/17.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:5671d3eb-018b-4925-ab50-d84c33c269cf
```
  - 18.kmac_long_msg_and_output.110221709866501172162020200260704986307717438576080974881079886665214276633703
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/18.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:b102a121-8873-43d5-8f69-845c130e690f
```
UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 1 failures:
- Test kmac_error has 1 failures.
  - 14.kmac_error.103084509960579810098912844159539732130652259405409045299581533233845074707073
    Line 790, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_error/latest/run.log
```
  UVM_FATAL @ 10012016511 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 10012016511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```