KMAC/MASKED Simulation Results

Wednesday July 03 2024 23:02:32 UTC

GitHub Revision: e6706fcc7b

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 8083624550445280117614176890238357255195852125596561370221115831648066795492

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.626m	5.736ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.140s	98.604us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.240s	30.809us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	21.880s	2.956ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.020s	691.775us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.910s	324.596us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.240s	30.809us	20	20	100.00
		kmac_csr_aliasing	10.020s	691.775us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.820s	12.848us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.480s	38.045us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	58.624m	517.551ms	50	50	100.00
V2	burst_write	kmac_burst_write	27.320m	28.714ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	42.954m	733.419ms	50	50	100.00
		kmac_test_vectors_sha3_256	39.438m	1.138s	50	50	100.00
		kmac_test_vectors_sha3_384	33.608m	873.201ms	50	50	100.00
		kmac_test_vectors_sha3_512	23.421m	344.543ms	50	50	100.00
		kmac_test_vectors_shake_128	1.903h	1.070s	50	50	100.00
		kmac_test_vectors_shake_256	1.860h	4.374s	50	50	100.00
		kmac_test_vectors_kmac	7.400s	426.484us	50	50	100.00
		kmac_test_vectors_kmac_xof	7.340s	1.999ms	50	50	100.00
V2	sideload	kmac_sideload	9.569m	12.034ms	50	50	100.00
V2	app	kmac_app	6.944m	52.736ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.515m	20.130ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	7.936m	76.806ms	47	50	94.00
V2	error	kmac_error	8.816m	56.562ms	50	50	100.00
V2	key_error	kmac_key_error	14.890s	7.327ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	43.670s	6.321ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	38.590s	1.666ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.248m	7.036ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	57.930s	1.377ms	50	50	100.00
V2	stress_all	kmac_stress_all	1.006h	103.375ms	50	50	100.00
V2	intr_test	kmac_intr_test	0.900s	185.229us	50	50	100.00
V2	alert_test	kmac_alert_test	0.950s	83.300us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.450s	472.528us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.450s	472.528us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.140s	98.604us	5	5	100.00
		kmac_csr_rw	1.240s	30.809us	20	20	100.00
		kmac_csr_aliasing	10.020s	691.775us	5	5	100.00
		kmac_same_csr_outstanding	2.520s	136.014us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.140s	98.604us	5	5	100.00
		kmac_csr_rw	1.240s	30.809us	20	20	100.00
		kmac_csr_aliasing	10.020s	691.775us	5	5	100.00
		kmac_same_csr_outstanding	2.520s	136.014us	20	20	100.00
V2		TOTAL			1047	1050	99.71
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.340s	47.357us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.340s	47.357us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.340s	47.357us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.340s	47.357us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.110s	510.980us	15	20	75.00
V2S	tl_intg_err	kmac_sec_cm	1.834m	9.781ms	5	5	100.00
		kmac_tl_intg_err	5.000s	694.301us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.000s	694.301us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	57.930s	1.377ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.626m	5.736ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	9.569m	12.034ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.340s	47.357us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.834m	9.781ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.834m	9.781ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.834m	9.781ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.626m	5.736ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	57.930s	1.377ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.834m	9.781ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	7.140m	26.165ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.626m	5.736ms	50	50	100.00
V2S		TOTAL			70	75	93.33
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	44.585m	204.351ms	1	10	10.00
V3		TOTAL			1	10	10.00
		TOTAL			1233	1250	98.64

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	24	96.00
V2S	5	5	4	80.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.28	97.91	92.58	99.51	77.46	95.59	99.05	97.88

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:825) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 8 failures:

  • Test kmac_stress_all_with_rand_reset has 8 failures.

    • 0.kmac_stress_all_with_rand_reset.61450057088012532017635082247877027644593129566782858102486409599155237985153
      Line 1149, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 99858005810 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 99858005810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.kmac_stress_all_with_rand_reset.89571737560561017128596537776917188341845180671722549264949571439962666397658
      Line 519, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 69806723150 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 69806723150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 6 more failures.

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: * Check_csr_read_clear_staged_val task: check update_err status has 5 failures:

  • Test kmac_shadow_reg_errors_with_csr_rw has 5 failures.

    • 1.kmac_shadow_reg_errors_with_csr_rw.105740533965314305346655593615822543881067689149885858552430379467353671660060
      Line 255, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

        UVM_ERROR @  64822401 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
        UVM_INFO @  64822401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 10.kmac_shadow_reg_errors_with_csr_rw.97105432814280224502302566736140778447720524899014942978416984076927789321892
      Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/10.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

        UVM_ERROR @  49983445 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
        UVM_INFO @  49983445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 3 more failures.

• UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 1.kmac_stress_all_with_rand_reset.90015422677893683557593933347316105134038142385601899062907943886914340659415
      Line 2025, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 71144233314 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483704 [0x80000038]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 71144233314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 1 failures:

  • Test kmac_entropy_refresh has 1 failures.

    • 6.kmac_entropy_refresh.33286043875714468720226768497069378901251149496227517917217860114771061450300
      Line 390, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_entropy_refresh/latest/run.log

        UVM_ERROR @ 10719472764 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
        UVM_INFO @ 10719472764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test kmac_entropy_refresh has 1 failures.

    • 37.kmac_entropy_refresh.51949294771087218531282363502853621237489681552613578729835211996167152602702
      Line 1137, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/37.kmac_entropy_refresh/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 1 failures:

  • Test kmac_entropy_refresh has 1 failures.

    • 41.kmac_entropy_refresh.76418082409979915432147574514453997700514062076183205269009712912216154563435
      Line 475, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/41.kmac_entropy_refresh/latest/run.log

        UVM_FATAL @ 1768633947 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (3 [0x3] vs 93 [0x5d]) Mismatch between unmasked_digest[0] and dpi_digest[0]
        UVM_INFO @ 1768633947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.07.03_01.47.44
• 2024.07.02_10.43.12
• 2024.07.02_04.12.36
• 2024.07.01_10.57.30
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