KMAC/MASKED Simulation Results

Monday July 01 2024 23:02:26 UTC

GitHub Revision: `e9ae10fb42`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 81071883735317974084005537723499931298658500385730214730015283368929474034200

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.648m	28.166ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.160s	99.885us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.240s	39.304us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	19.540s	3.591ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.500s	2.147ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.550s	320.143us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.240s	39.304us	20	20	100.00
		kmac_csr_aliasing	10.500s	2.147ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.800s	29.657us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.450s	38.205us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	54.294m	232.061ms	50	50	100.00
V2	burst_write	kmac_burst_write	26.784m	60.743ms	48	50	96.00
V2	test_vectors	kmac_test_vectors_sha3_224	43.226m	273.079ms	50	50	100.00
		kmac_test_vectors_sha3_256	41.288m	430.528ms	50	50	100.00
		kmac_test_vectors_sha3_384	33.761m	280.193ms	50	50	100.00
		kmac_test_vectors_sha3_512	24.658m	339.034ms	50	50	100.00
		kmac_test_vectors_shake_128	1.851h	1.100s	50	50	100.00
		kmac_test_vectors_shake_256	1.544h	2.148s	48	50	96.00
		kmac_test_vectors_kmac	7.380s	664.997us	50	50	100.00
		kmac_test_vectors_kmac_xof	7.650s	547.167us	49	50	98.00
V2	sideload	kmac_sideload	8.873m	21.530ms	50	50	100.00
V2	app	kmac_app	7.309m	17.890ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.688m	49.488ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	7.295m	84.864ms	49	50	98.00
V2	error	kmac_error	8.708m	19.250ms	50	50	100.00
V2	key_error	kmac_key_error	14.310s	3.659ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	54.260s	2.258ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	45.270s	1.509ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.430m	16.608ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	1.257m	1.022ms	50	50	100.00
V2	stress_all	kmac_stress_all	41.320m	138.562ms	47	50	94.00
V2	intr_test	kmac_intr_test	0.860s	31.511us	50	50	100.00
V2	alert_test	kmac_alert_test	0.930s	51.393us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.080s	557.935us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.080s	557.935us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.160s	99.885us	5	5	100.00
		kmac_csr_rw	1.240s	39.304us	20	20	100.00
		kmac_csr_aliasing	10.500s	2.147ms	5	5	100.00
		kmac_same_csr_outstanding	2.600s	115.433us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.160s	99.885us	5	5	100.00
		kmac_csr_rw	1.240s	39.304us	20	20	100.00
		kmac_csr_aliasing	10.500s	2.147ms	5	5	100.00
		kmac_same_csr_outstanding	2.600s	115.433us	20	20	100.00
V2		TOTAL			1041	1050	99.14
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.560s	58.045us	17	20	85.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.560s	58.045us	17	20	85.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.560s	58.045us	17	20	85.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.560s	58.045us	17	20	85.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.140s	152.365us	18	20	90.00
V2S	tl_intg_err	kmac_sec_cm	1.393m	10.169ms	5	5	100.00
		kmac_tl_intg_err	5.280s	335.556us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.280s	335.556us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.257m	1.022ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.648m	28.166ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	8.873m	21.530ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.560s	58.045us	17	20	85.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.393m	10.169ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.393m	10.169ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.393m	10.169ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.648m	28.166ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.257m	1.022ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.393m	10.169ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.917m	33.266ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.648m	28.166ms	50	50	100.00
V2S		TOTAL			70	75	93.33
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	23.784m	194.382ms	4	10	40.00
V3		TOTAL			4	10	40.00
		TOTAL			1230	1250	98.40

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	20	80.00
V2S	5	5	3	60.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.25	97.91	92.65	99.89	76.76	95.59	99.05	97.88

Failure Buckets

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: * Check_csr_read_clear_staged_val task: check update_err status has 5 failures:

Test kmac_shadow_reg_errors_with_csr_rw has 2 failures.

1.kmac_shadow_reg_errors_with_csr_rw.89271312890864488791263632101693984567047049389303225950139038825852363876973
Line 255, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @ 314720070 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @ 314720070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

17.kmac_shadow_reg_errors_with_csr_rw.112257368121015862975807570927542801944427550746937828135582493521805455212981
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/17.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  37480760 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  37480760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_shadow_reg_errors has 3 failures.

3.kmac_shadow_reg_errors.21400499291739707130416314580174200755436369373057389081064424063450753249667
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @  36247605 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  36247605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.kmac_shadow_reg_errors.102228080778685280410428907068486316721351390482736520796314049033263528800575
Line 255, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @  18989482 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  18989482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (cip_base_vseq.sv:828) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 4 failures:
- Test kmac_stress_all_with_rand_reset has 4 failures.
  - 1.kmac_stress_all_with_rand_reset.65404440501914894273361650375091071820817910820414856795974121348450292931291
    Line 1242, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 38103745679 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 38103745679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.kmac_stress_all_with_rand_reset.104508587508979625845703044119314241283670336511010340861402284225957505701823
    Line 399, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2866740670 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2866740670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 3 failures:

Test kmac_entropy_refresh has 1 failures.

4.kmac_entropy_refresh.1091482341388047201399172461976543502996220078627967913498829357963052394993
Line 257, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 276325597 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (231 [0xe7] vs 213 [0xd5]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 276325597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 2 failures.

24.kmac_stress_all.31384778578431487464270451306372502711666103299452068757533565223258135260136
Line 601, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/24.kmac_stress_all/latest/run.log

  UVM_FATAL @ 6919027771 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (111 [0x6f] vs 78 [0x4e]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 6919027771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

27.kmac_stress_all.3059333516327222754690040408851170842326113097764788892346490537129805244767
Line 377, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/27.kmac_stress_all/latest/run.log

  UVM_FATAL @ 1897868970 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (159 [0x9f] vs 52 [0x34]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 1897868970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 3 failures:
- Test kmac_test_vectors_kmac_xof has 1 failures.
  - 20.kmac_test_vectors_kmac_xof.19474242429604385130969528415787628981025061623320180697905981367779771232191
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/20.kmac_test_vectors_kmac_xof/latest/run.log
```
  UVM_ERROR @ 176057361 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 176057361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_shake_256 has 2 failures.
  - 26.kmac_test_vectors_shake_256.56697192100421692274940096178696410091478395610772787810830624880381034780875
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/26.kmac_test_vectors_shake_256/latest/run.log
```
  UVM_ERROR @  89723952 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  89723952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 44.kmac_test_vectors_shake_256.16428313336764753319854881233596405602042178069042088150159847500184907003523
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/44.kmac_test_vectors_shake_256/latest/run.log
```
  UVM_ERROR @  75472811 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  75472811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 2 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 6.kmac_stress_all_with_rand_reset.84123788758429917227143012449208998765481743278952731537649946598860080753413
    Line 812, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 28708118913 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 28708118913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_stress_all has 1 failures.
  - 44.kmac_stress_all.112267991347578960388170498557509747090741243244978212089595441098685020856240
    Line 1022, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/44.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 32612044238 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 32612044238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test kmac_burst_write has 2 failures.
  - 11.kmac_burst_write.37492627115752240403060180124016861210352909079952022368183413055621356896301
    Line 806, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 17.kmac_burst_write.6185784458613319038930924488406260034077902289601657414460427710339280545919
    Line 800, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/17.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 9.kmac_stress_all_with_rand_reset.87830771987527885372717495093008412738183133872278856143725760704280253630366
    Line 300, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1894676336 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483672 [0x80000018]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 1894676336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```