KMAC/MASKED Simulation Results

Tuesday July 02 2024 14:17:13 UTC

GitHub Revision: `abd7ce57f2`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 7120396591488306882161367642496372905152431708445539866860566607772054886363

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.490m	4.981ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.090s	90.791us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.240s	36.852us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	22.080s	4.793ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.360s	387.621us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.580s	39.431us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.240s	36.852us	20	20	100.00
		kmac_csr_aliasing	9.360s	387.621us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.780s	23.938us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.420s	21.705us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	57.054m	150.935ms	49	50	98.00
V2	burst_write	kmac_burst_write	26.579m	14.384ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	44.661m	980.797ms	50	50	100.00
		kmac_test_vectors_sha3_256	42.062m	761.629ms	50	50	100.00
		kmac_test_vectors_sha3_384	33.325m	287.882ms	49	50	98.00
		kmac_test_vectors_sha3_512	24.434m	207.884ms	49	50	98.00
		kmac_test_vectors_shake_128	1.872h	1.085s	50	50	100.00
		kmac_test_vectors_shake_256	1.796h	3.117s	50	50	100.00
		kmac_test_vectors_kmac	7.570s	263.886us	50	50	100.00
		kmac_test_vectors_kmac_xof	7.100s	1.223ms	50	50	100.00
V2	sideload	kmac_sideload	9.269m	82.010ms	50	50	100.00
V2	app	kmac_app	6.973m	18.552ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.806m	71.149ms	9	10	90.00
V2	entropy_refresh	kmac_entropy_refresh	7.010m	17.859ms	49	50	98.00
V2	error	kmac_error	8.733m	23.789ms	49	50	98.00
V2	key_error	kmac_key_error	19.670s	19.663ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	45.200s	6.880ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	39.750s	1.301ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	53.980s	18.275ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	54.620s	7.552ms	50	50	100.00
V2	stress_all	kmac_stress_all	52.910m	104.120ms	47	50	94.00
V2	intr_test	kmac_intr_test	0.860s	89.542us	50	50	100.00
V2	alert_test	kmac_alert_test	0.900s	126.729us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.320s	486.233us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.320s	486.233us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.090s	90.791us	5	5	100.00
		kmac_csr_rw	1.240s	36.852us	20	20	100.00
		kmac_csr_aliasing	9.360s	387.621us	5	5	100.00
		kmac_same_csr_outstanding	2.820s	1.011ms	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.090s	90.791us	5	5	100.00
		kmac_csr_rw	1.240s	36.852us	20	20	100.00
		kmac_csr_aliasing	9.360s	387.621us	5	5	100.00
		kmac_same_csr_outstanding	2.820s	1.011ms	20	20	100.00
V2		TOTAL			1041	1050	99.14
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.520s	311.508us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.520s	311.508us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.520s	311.508us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.520s	311.508us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.190s	2.084ms	18	20	90.00
V2S	tl_intg_err	kmac_sec_cm	1.483m	7.880ms	5	5	100.00
		kmac_tl_intg_err	5.270s	4.764ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.270s	4.764ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	54.620s	7.552ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.490m	4.981ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	9.269m	82.010ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.520s	311.508us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.483m	7.880ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.483m	7.880ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.483m	7.880ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.490m	4.981ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	54.620s	7.552ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.483m	7.880ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.558m	12.353ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.490m	4.981ms	50	50	100.00
V2S		TOTAL			73	75	97.33
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	38.918m	39.750ms	2	10	20.00
V3		TOTAL			2	10	20.00
		TOTAL			1231	1250	98.48

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	18	72.00
V2S	5	5	4	80.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.50	97.89	92.55	99.89	78.87	95.53	98.89	97.88

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 7 failures:
- Test kmac_stress_all_with_rand_reset has 7 failures.
  - 0.kmac_stress_all_with_rand_reset.63423018666975959658296180320094049955967481644359402849582444381588472251581
    Line 595, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 30747872674 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 30747872674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.113229469929246054050055938823613955786855143376591405888851288604062749251331
    Line 269, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 846912202 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 846912202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 4 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 7.kmac_stress_all_with_rand_reset.112948772756868020302860014176882149617799974650382454099084294153481581942525
    Line 733, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 11634615442 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 11634615442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_stress_all has 2 failures.
  - 9.kmac_stress_all.47062801074714394051014006631957772578568675319040063439973409250170445618282
    Line 594, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 34874142061 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 34874142061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 48.kmac_stress_all.4613020992775326628298236637907642143084575956239578792886266016632095204762
    Line 927, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/48.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 61402226661 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 61402226661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_error has 1 failures.
  - 16.kmac_error.108689765156234677095530264526690042207545874733842687827511830041553704404625
    Line 714, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/16.kmac_error/latest/run.log
```
  UVM_FATAL @ 10086106322 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 10086106322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 3 failures:
- Test kmac_test_vectors_sha3_384 has 1 failures.
  - 19.kmac_test_vectors_sha3_384.78449360898672786640531919493556783683244431746189563851152673933791283999726
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_test_vectors_sha3_384/latest/run.log
```
  UVM_ERROR @  34553247 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  34553247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_sha3_512 has 1 failures.
  - 28.kmac_test_vectors_sha3_512.113560823148903990880219297013589705434636270194729435221260502055411566347247
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/28.kmac_test_vectors_sha3_512/latest/run.log
```
  UVM_ERROR @  99701744 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  99701744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_stress_all has 1 failures.
  - 38.kmac_stress_all.3147673499920420538664720751950132824204929175168360696147481052855045909413
    Line 1692, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/38.kmac_stress_all/latest/run.log
```
  UVM_ERROR @ 83714745295 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 83714745295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 2 failures:
- Test kmac_app_with_partial_data has 1 failures.
  - 6.kmac_app_with_partial_data.7952836766767762305578185863142121755560606446603428992776026149657331819446
    Line 377, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_app_with_partial_data/latest/run.log
```
  UVM_FATAL @ 16946744964 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (152 [0x98] vs 63 [0x3f]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 16946744964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_entropy_refresh has 1 failures.
  - 39.kmac_entropy_refresh.96670368858808815213273644200971502088665987438413337975303094764111736263298
    Line 407, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/39.kmac_entropy_refresh/latest/run.log
```
  UVM_FATAL @ 23093811889 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (151 [0x97] vs 136 [0x88]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 23093811889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: * Check_csr_read_clear_staged_val task: check update_err status has 2 failures:
- Test kmac_shadow_reg_errors_with_csr_rw has 2 failures.
  - 6.kmac_shadow_reg_errors_with_csr_rw.98925344699271182871363770027756326678840315413262269855910026813575886049562
    Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @  97916562 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  97916562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 10.kmac_shadow_reg_errors_with_csr_rw.54542025904974323136878398234480954339001143137390477747886095664545612291586
    Line 255, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/10.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @  85006916 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  85006916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job kmac_masked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test kmac_long_msg_and_output has 1 failures.
  - 8.kmac_long_msg_and_output.79608739788639394903919677107903909511471709417056646290732432998036142098942
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:d91c4301-0268-4f14-809a-f7dd4357af3a
```

KMAC/MASKED Simulation Results

Tuesday July 02 2024 14:17:13 UTC

GitHub Revision: abd7ce57f2

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 7120396591488306882161367642496372905152431708445539866860566607772054886363

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `abd7ce57f2`