KMAC/MASKED Simulation Results

Tuesday July 16 2024 23:15:02 UTC

GitHub Revision: `aad711e1bc`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 38297581588405771015102977205739484163575733999253050480227719508149669635625

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.484m	8.671ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.210s	34.426us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.250s	62.836us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	19.050s	12.143ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.640s	534.167us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.870s	128.339us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.250s	62.836us	20	20	100.00
		kmac_csr_aliasing	9.640s	534.167us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.770s	29.612us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.500s	67.070us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	57.093m	496.412ms	50	50	100.00
V2	burst_write	kmac_burst_write	24.674m	31.264ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	46.447m	1.387s	50	50	100.00
		kmac_test_vectors_sha3_256	42.705m	389.834ms	50	50	100.00
		kmac_test_vectors_sha3_384	31.676m	220.127ms	49	50	98.00
		kmac_test_vectors_sha3_512	23.833m	486.979ms	50	50	100.00
		kmac_test_vectors_shake_128	1.748h	1.638s	50	50	100.00
		kmac_test_vectors_shake_256	1.759h	4.343s	50	50	100.00
		kmac_test_vectors_kmac	7.440s	455.726us	50	50	100.00
		kmac_test_vectors_kmac_xof	8.620s	978.636us	50	50	100.00
V2	sideload	kmac_sideload	9.103m	6.164ms	50	50	100.00
V2	app	kmac_app	6.634m	22.914ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.060m	26.730ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	7.133m	38.240ms	48	50	96.00
V2	error	kmac_error	9.740m	81.664ms	49	50	98.00
V2	key_error	kmac_key_error	14.100s	4.157ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	50.510s	1.413ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	56.070s	3.829ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.233m	32.196ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	56.890s	1.050ms	50	50	100.00
V2	stress_all	kmac_stress_all	54.467m	175.911ms	47	50	94.00
V2	intr_test	kmac_intr_test	0.890s	17.172us	50	50	100.00
V2	alert_test	kmac_alert_test	0.950s	17.568us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.660s	293.862us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.660s	293.862us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.210s	34.426us	5	5	100.00
		kmac_csr_rw	1.250s	62.836us	20	20	100.00
		kmac_csr_aliasing	9.640s	534.167us	5	5	100.00
		kmac_same_csr_outstanding	2.670s	121.512us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.210s	34.426us	5	5	100.00
		kmac_csr_rw	1.250s	62.836us	20	20	100.00
		kmac_csr_aliasing	9.640s	534.167us	5	5	100.00
		kmac_same_csr_outstanding	2.670s	121.512us	20	20	100.00
V2		TOTAL			1042	1050	99.24
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.530s	77.350us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.530s	77.350us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.530s	77.350us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.530s	77.350us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.010s	258.923us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.791m	77.985ms	5	5	100.00
		kmac_tl_intg_err	5.280s	187.196us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.280s	187.196us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	56.890s	1.050ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.484m	8.671ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	9.103m	6.164ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.530s	77.350us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.791m	77.985ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.791m	77.985ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.791m	77.985ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.484m	8.671ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	56.890s	1.050ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.791m	77.985ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	7.089m	17.732ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.484m	8.671ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	21.704m	19.479ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1232	1250	98.56

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	20	80.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.92	97.80	91.03	99.89	76.76	95.17	98.89	97.88

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 8 failures:
- Test kmac_stress_all_with_rand_reset has 8 failures.
  - 0.kmac_stress_all_with_rand_reset.107814033427059087712163571373061276991619454922954873719475557502121016564879
    Line 999, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 19478861044 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 19478861044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.97164472047613712943687217847838765551773172589684484298963545896821912118342
    Line 420, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3241828115 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3241828115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 5 failures:

Test kmac_stress_all has 2 failures.

7.kmac_stress_all.109492640723410959648586653837880281619061412591001408242674516315623476467462
Line 281, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_stress_all/latest/run.log

  UVM_FATAL @ 313808010 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (105 [0x69] vs 134 [0x86]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 313808010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

27.kmac_stress_all.101517680966361766984948543728467345108090371238112641934705814225572578996095
Line 535, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/27.kmac_stress_all/latest/run.log

  UVM_FATAL @ 3779231905 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (133 [0x85] vs 107 [0x6b]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 3779231905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 2 failures.

29.kmac_entropy_refresh.29036783879789020289138490927142709071919733769719887282423719921034086393674
Line 941, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/29.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 5949052470 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (248 [0xf8] vs 226 [0xe2]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 5949052470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

44.kmac_entropy_refresh.113304058879503616043789820289655460770952791885416390316685320546791794279943
Line 373, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/44.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 2173783953 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (199 [0xc7] vs 100 [0x64]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 2173783953 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app has 1 failures.

33.kmac_app.107831816773270528568862617790610178417573340319134154635341387366645650609598
Line 503, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/33.kmac_app/latest/run.log

  UVM_FATAL @ 1726158239 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (1 [0x1] vs 227 [0xe3]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 1726158239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 2 failures:
- Test kmac_stress_all_with_rand_reset has 2 failures.
  - 7.kmac_stress_all_with_rand_reset.101386504757044919724183465504330060784853661088819913922608408886164583972681
    Line 1882, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 36851433081 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483760 [0x80000070]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 36851433081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.kmac_stress_all_with_rand_reset.39361550015918254656954259019286505419528793035380248887574755957433639479025
    Line 593, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 18666043097 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483664 [0x80000010]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 18666043097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 2 failures:
- Test kmac_stress_all has 1 failures.
  - 14.kmac_stress_all.21809723285198935197787493267555420161582276539952038883888999697842649172235
    Line 1540, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 187062900764 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 187062900764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_error has 1 failures.
  - 38.kmac_error.66451998149059034517110496335461089249899282833671899938683106137523517016805
    Line 739, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/38.kmac_error/latest/run.log
```
  UVM_FATAL @ 10042581892 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 10042581892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 1 failures:
- Test kmac_test_vectors_sha3_384 has 1 failures.
  - 36.kmac_test_vectors_sha3_384.13865236838020947516770078280398018277733080842032244829244053636286493455288
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/36.kmac_test_vectors_sha3_384/latest/run.log
```
  UVM_ERROR @ 113965560 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 113965560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```