KMAC/MASKED Simulation Results

Wednesday July 17 2024 23:02:16 UTC

GitHub Revision: `8b2da8db5e`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 31877364624131593519988921539075110140045739991215723614576185349550879231344

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.595m	26.737ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.190s	103.864us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.240s	56.018us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	15.100s	373.817us	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.300s	1.079ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.640s	150.721us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.240s	56.018us	20	20	100.00
		kmac_csr_aliasing	10.300s	1.079ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.870s	44.793us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.450s	72.029us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	59.317m	130.213ms	50	50	100.00
V2	burst_write	kmac_burst_write	25.864m	56.309ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	46.001m	1.651s	50	50	100.00
		kmac_test_vectors_sha3_256	39.723m	95.478ms	50	50	100.00
		kmac_test_vectors_sha3_384	31.884m	261.652ms	50	50	100.00
		kmac_test_vectors_sha3_512	23.856m	710.138ms	49	50	98.00
		kmac_test_vectors_shake_128	1.754h	1.050s	50	50	100.00
		kmac_test_vectors_shake_256	1.450h	876.809ms	49	50	98.00
		kmac_test_vectors_kmac	7.280s	1.062ms	50	50	100.00
		kmac_test_vectors_kmac_xof	7.350s	1.843ms	50	50	100.00
V2	sideload	kmac_sideload	8.814m	16.416ms	50	50	100.00
V2	app	kmac_app	6.581m	11.566ms	48	50	96.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.510m	9.231ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	8.053m	156.481ms	49	50	98.00
V2	error	kmac_error	8.607m	121.341ms	46	50	92.00
V2	key_error	kmac_key_error	15.730s	11.207ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	47.680s	1.929ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	37.650s	1.732ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.274m	15.760ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	30.210s	2.650ms	50	50	100.00
V2	stress_all	kmac_stress_all	39.341m	80.731ms	44	50	88.00
V2	intr_test	kmac_intr_test	0.910s	38.388us	50	50	100.00
V2	alert_test	kmac_alert_test	0.970s	39.111us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.070s	1.549ms	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.070s	1.549ms	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.190s	103.864us	5	5	100.00
		kmac_csr_rw	1.240s	56.018us	20	20	100.00
		kmac_csr_aliasing	10.300s	1.079ms	5	5	100.00
		kmac_same_csr_outstanding	2.640s	653.184us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.190s	103.864us	5	5	100.00
		kmac_csr_rw	1.240s	56.018us	20	20	100.00
		kmac_csr_aliasing	10.300s	1.079ms	5	5	100.00
		kmac_same_csr_outstanding	2.640s	653.184us	20	20	100.00
V2		TOTAL			1035	1050	98.57
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.330s	176.757us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.330s	176.757us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.330s	176.757us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.330s	176.757us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.960s	491.096us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.978m	16.809ms	5	5	100.00
		kmac_tl_intg_err	5.630s	501.792us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.630s	501.792us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	30.210s	2.650ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.595m	26.737ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	8.814m	16.416ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.330s	176.757us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.978m	16.809ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.978m	16.809ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.978m	16.809ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.595m	26.737ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	30.210s	2.650ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.978m	16.809ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.614m	50.272ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.595m	26.737ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	51.953m	233.257ms	3	10	30.00
V3		TOTAL			3	10	30.00
		TOTAL			1228	1250	98.24

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	19	76.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.30	97.89	92.58	99.89	77.46	95.53	98.89	97.88

Failure Buckets

UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 6 failures:
- Test kmac_stress_all has 4 failures.
  - 19.kmac_stress_all.76567055219815169625747728177777220036830187588256363280721861197589279574960
    Line 1426, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 116441747509 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 116441747509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 21.kmac_stress_all.86545571076317486058634925438839284163544022315428017650308161259330544828690
    Line 1364, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/21.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 109448626831 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 109448626831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
- Test kmac_error has 2 failures.
  - 43.kmac_error.46388283770328172002972647038842600654382646597743904228820279176713561332706
    Line 349, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/43.kmac_error/latest/run.log
```
  UVM_FATAL @ 10048578140 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 10048578140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 45.kmac_error.25797691712799013245444127496366004920518491473767076239902121056902832449107
    Line 471, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/45.kmac_error/latest/run.log
```
  UVM_FATAL @ 10171132348 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 10171132348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:839) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 5 failures:
- Test kmac_stress_all_with_rand_reset has 5 failures.
  - 1.kmac_stress_all_with_rand_reset.31821849536552744911220364215504566157889540044909584386582345764852535301847
    Line 506, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 15930670499 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 15930670499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.kmac_stress_all_with_rand_reset.17258494655339282592947704815316221300625418937404737905473935214358848190424
    Line 280, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 829523748 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 829523748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 3 failures:

Test kmac_error has 1 failures.

5.kmac_error.96611922435053661291712540445788835808599179360881501384775929542025373059876
Line 408, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_error/latest/run.log

  UVM_FATAL @ 2835617518 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (179 [0xb3] vs 168 [0xa8]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 2835617518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app has 1 failures.

7.kmac_app.9436901816283784347734124041646341490755265789110243335888051209657318704356
Line 475, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_app/latest/run.log

  UVM_FATAL @ 7756477824 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (115 [0x73] vs 56 [0x38]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 7756477824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 1 failures.

13.kmac_stress_all.98659758905124365073435304020200392324029017069705028464986359973213488382944
Line 1599, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/13.kmac_stress_all/latest/run.log

  UVM_FATAL @ 250844425316 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (96 [0x60] vs 92 [0x5c]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 250844425316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
- Test kmac_entropy_refresh has 1 failures.
  - 28.kmac_entropy_refresh.54223409519078853851647573777142770010315669410631675877060755968574061112166
    Line 840, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/28.kmac_entropy_refresh/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_app has 1 failures.
  - 47.kmac_app.89414629644039675051760702670170450645023666945398042363219435482019797788405
    Line 1074, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/47.kmac_app/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_error has 1 failures.
  - 49.kmac_error.37366277660030684897003435498234130433238141478571266653395771060785418554071
    Line 893, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/49.kmac_error/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 3 failures:
- Test kmac_test_vectors_sha3_512 has 1 failures.
  - 38.kmac_test_vectors_sha3_512.27215360713019862232605980695219307519874635854334745532123267326427754387402
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/38.kmac_test_vectors_sha3_512/latest/run.log
```
  UVM_ERROR @ 123927758 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 123927758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_shake_256 has 1 failures.
  - 38.kmac_test_vectors_shake_256.53211213578604899692035520256245624506363330513837241706929305545838934782954
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/38.kmac_test_vectors_shake_256/latest/run.log
```
  UVM_ERROR @  28999694 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  28999694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_stress_all has 1 failures.
  - 41.kmac_stress_all.91423261418551443170752114869895957873368252072583261207912764007600758845598
    Line 2901, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/41.kmac_stress_all/latest/run.log
```
  UVM_ERROR @ 64981276431 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 64981276431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 2 failures:
- Test kmac_stress_all_with_rand_reset has 2 failures.
  - 5.kmac_stress_all_with_rand_reset.87746178963298470324581223189142406621049985181645680285968402655701268570250
    Line 2756, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 260246745925 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483680 [0x80000020]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 260246745925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.kmac_stress_all_with_rand_reset.89114090781437284730266241304707962791489834727527822510586732860107614548874
    Line 1097, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 27086119585 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483752 [0x80000068]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 27086119585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```