KMAC/MASKED Simulation Results

Thursday July 18 2024 23:02:12 UTC

GitHub Revision: `974aaab627`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 46057207235241274571178436692064798722168129065126426307050395083305588858879

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.519m	10.010ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.210s	51.537us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.200s	31.523us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	21.290s	3.504ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	8.450s	721.354us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.580s	68.348us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.200s	31.523us	20	20	100.00
		kmac_csr_aliasing	8.450s	721.354us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.770s	12.587us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.500s	34.705us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	54.584m	257.279ms	50	50	100.00
V2	burst_write	kmac_burst_write	27.124m	54.675ms	48	50	96.00
V2	test_vectors	kmac_test_vectors_sha3_224	46.386m	1.917s	50	50	100.00
		kmac_test_vectors_sha3_256	44.019m	1.330s	50	50	100.00
		kmac_test_vectors_sha3_384	30.865m	291.215ms	50	50	100.00
		kmac_test_vectors_sha3_512	23.372m	661.036ms	50	50	100.00
		kmac_test_vectors_shake_128	1.965h	3.235s	49	50	98.00
		kmac_test_vectors_shake_256	1.595h	2.496s	50	50	100.00
		kmac_test_vectors_kmac	7.890s	4.222ms	50	50	100.00
		kmac_test_vectors_kmac_xof	7.220s	559.079us	49	50	98.00
V2	sideload	kmac_sideload	9.239m	48.296ms	50	50	100.00
V2	app	kmac_app	6.648m	195.434ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.568m	6.172ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	7.389m	69.573ms	48	50	96.00
V2	error	kmac_error	7.723m	20.287ms	49	50	98.00
V2	key_error	kmac_key_error	16.080s	6.843ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	47.970s	2.360ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	39.230s	2.018ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.509m	33.394ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	54.750s	3.909ms	50	50	100.00
V2	stress_all	kmac_stress_all	53.239m	100.333ms	48	50	96.00
V2	intr_test	kmac_intr_test	0.880s	13.918us	50	50	100.00
V2	alert_test	kmac_alert_test	0.940s	20.883us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.330s	53.242us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.330s	53.242us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.210s	51.537us	5	5	100.00
		kmac_csr_rw	1.200s	31.523us	20	20	100.00
		kmac_csr_aliasing	8.450s	721.354us	5	5	100.00
		kmac_same_csr_outstanding	2.720s	483.086us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.210s	51.537us	5	5	100.00
		kmac_csr_rw	1.200s	31.523us	20	20	100.00
		kmac_csr_aliasing	8.450s	721.354us	5	5	100.00
		kmac_same_csr_outstanding	2.720s	483.086us	20	20	100.00
V2		TOTAL			1041	1050	99.14
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.570s	116.011us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.570s	116.011us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.570s	116.011us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.570s	116.011us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.990s	503.544us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.817m	67.207ms	5	5	100.00
		kmac_tl_intg_err	5.370s	1.216ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.370s	1.216ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	54.750s	3.909ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.519m	10.010ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	9.239m	48.296ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.570s	116.011us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.817m	67.207ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.817m	67.207ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.817m	67.207ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.519m	10.010ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	54.750s	3.909ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.817m	67.207ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	7.142m	47.098ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.519m	10.010ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	54.710m	179.910ms	3	10	30.00
V3		TOTAL			3	10	30.00
		TOTAL			1234	1250	98.72

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	19	76.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.33	97.91	92.65	99.89	77.46	95.59	99.05	97.73

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:839) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 5 failures:
- Test kmac_stress_all_with_rand_reset has 5 failures.
  - 0.kmac_stress_all_with_rand_reset.29155899712156817933253124533995340965251219726279465078615829263639056601713
    Line 1538, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 84417506961 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 84417506961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.51718444207920965573554598332435685312175565616843720079562913867774062479851
    Line 258, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 345045328 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 345045328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
- Test kmac_error has 1 failures.
  - 7.kmac_error.524861090118916451420573874441507700773797894186487926156369965667482027120
    Line 774, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_error/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_burst_write has 2 failures.
  - 24.kmac_burst_write.60996679586276556059661216617250624708699887333008624630996569024445755261841
    Line 860, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/24.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 38.kmac_burst_write.5034802210808320395846772173212941050690164925596797837396154755143392341602
    Line 782, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/38.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 3 failures:

Test kmac_stress_all has 1 failures.

32.kmac_stress_all.102516536830466197229766888444996791617849507133418559446319474943663170384723
Line 417, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/32.kmac_stress_all/latest/run.log

  UVM_FATAL @ 17225150503 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (202 [0xca] vs 141 [0x8d]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 17225150503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 2 failures.

38.kmac_entropy_refresh.17606348458333647382599759678804501308510781282459830967575644275573593892272
Line 447, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/38.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 17156872591 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (244 [0xf4] vs 46 [0x2e]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 17156872591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

49.kmac_entropy_refresh.71092810528334331306528516559987635340609250776407642922446273983517759702855
Line 343, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/49.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 579055268 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (211 [0xd3] vs 251 [0xfb]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 579055268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 2 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 5.kmac_stress_all_with_rand_reset.14310692778839496143722911306435545169825846564755151287256789205241243373945
    Line 5167, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 179909944640 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 179909944640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_stress_all has 1 failures.
  - 44.kmac_stress_all.88915101742970132819412361869600380401282523452317252934535558125174518022182
    Line 1082, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/44.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 96049201170 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 96049201170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 2 failures:
- Test kmac_test_vectors_kmac_xof has 1 failures.
  - 9.kmac_test_vectors_kmac_xof.61731194037846636360408605427675318955669924916084333810698731486866329116498
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_test_vectors_kmac_xof/latest/run.log
```
  UVM_ERROR @  52423426 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  52423426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_shake_128 has 1 failures.
  - 42.kmac_test_vectors_shake_128.2928998831665651922383264171803824719059991325142419144621917189595748649691
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/42.kmac_test_vectors_shake_128/latest/run.log
```
  UVM_ERROR @  34215470 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  34215470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 8.kmac_stress_all_with_rand_reset.41938962085249343873348827918449943766545591338048994285464690444216183509863
    Line 262, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 263370733 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483712 [0x80000040]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 263370733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```