KMAC/MASKED Simulation Results

Sunday July 21 2024 23:02:06 UTC

GitHub Revision: `e971cd9798`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 60538554475599760039478308558126864941531727393021608909386829062452482962039

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.555m	28.076ms	49	50	98.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.160s	30.590us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.230s	28.141us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	18.730s	2.012ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.170s	1.524ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.710s	366.818us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.230s	28.141us	20	20	100.00
		kmac_csr_aliasing	9.170s	1.524ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.800s	26.045us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.500s	69.387us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	long_msg_and_output	kmac_long_msg_and_output	54.518m	386.977ms	50	50	100.00
V2	burst_write	kmac_burst_write	28.541m	15.246ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	45.105m	489.520ms	49	50	98.00
		kmac_test_vectors_sha3_256	40.132m	626.547ms	50	50	100.00
		kmac_test_vectors_sha3_384	32.111m	857.045ms	49	50	98.00
		kmac_test_vectors_sha3_512	23.907m	53.251ms	49	50	98.00
		kmac_test_vectors_shake_128	1.713h	265.896ms	50	50	100.00
		kmac_test_vectors_shake_256	1.806h	3.152s	50	50	100.00
		kmac_test_vectors_kmac	7.650s	1.123ms	50	50	100.00
		kmac_test_vectors_kmac_xof	7.520s	657.839us	50	50	100.00
V2	sideload	kmac_sideload	9.631m	44.669ms	50	50	100.00
V2	app	kmac_app	6.165m	5.624ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.262m	40.466ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	6.838m	113.997ms	49	50	98.00
V2	error	kmac_error	9.315m	15.218ms	50	50	100.00
V2	key_error	kmac_key_error	13.760s	7.136ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	47.920s	6.021ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	42.510s	2.789ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.241m	12.578ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	54.480s	13.142ms	50	50	100.00
V2	stress_all	kmac_stress_all	42.678m	134.514ms	49	50	98.00
V2	intr_test	kmac_intr_test	0.920s	16.319us	50	50	100.00
V2	alert_test	kmac_alert_test	0.960s	58.143us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.290s	258.324us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.290s	258.324us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.160s	30.590us	5	5	100.00
		kmac_csr_rw	1.230s	28.141us	20	20	100.00
		kmac_csr_aliasing	9.170s	1.524ms	5	5	100.00
		kmac_same_csr_outstanding	2.780s	479.686us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.160s	30.590us	5	5	100.00
		kmac_csr_rw	1.230s	28.141us	20	20	100.00
		kmac_csr_aliasing	9.170s	1.524ms	5	5	100.00
		kmac_same_csr_outstanding	2.780s	479.686us	20	20	100.00
V2		TOTAL			1045	1050	99.52
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.460s	85.872us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.460s	85.872us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.460s	85.872us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.460s	85.872us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.110s	1.068ms	19	20	95.00
V2S	tl_intg_err	kmac_sec_cm	1.967m	7.253ms	5	5	100.00
		kmac_tl_intg_err	5.310s	1.596ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.310s	1.596ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	54.480s	13.142ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.555m	28.076ms	49	50	98.00
V2S	sec_cm_key_sideload	kmac_sideload	9.631m	44.669ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.460s	85.872us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.967m	7.253ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.967m	7.253ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.967m	7.253ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.555m	28.076ms	49	50	98.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	54.480s	13.142ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.967m	7.253ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	7.294m	29.920ms	9	10	90.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.555m	28.076ms	49	50	98.00
V2S		TOTAL			73	75	97.33
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	27.318m	327.341ms	2	10	20.00
V3		TOTAL			2	10	20.00
		TOTAL			1234	1250	98.72

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	25	25	20	80.00
V2S	5	5	3	60.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.34	97.91	92.62	99.89	77.46	95.59	99.05	97.88

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:839) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 6 failures:
- Test kmac_stress_all_with_rand_reset has 6 failures.
  - 1.kmac_stress_all_with_rand_reset.105189579142478134529981125114281817943860826086475677752829003556004304889252
    Line 767, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9780503932 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 9780503932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.kmac_stress_all_with_rand_reset.61972506018744735315033083514626430429509497236757744511443275771940232301622
    Line 1021, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 118975380341 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 118975380341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 5 failures:

Test kmac_mubi has 1 failures.

2.kmac_mubi.50223437109349403012958962020471871893525233715019626176451103353727761405318
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_mubi/latest/run.log

  UVM_ERROR @  60117416 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  60117416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_test_vectors_sha3_512 has 1 failures.

3.kmac_test_vectors_sha3_512.27764930978167654829472085383385934633643227479294951138434628486023784415409
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_512/latest/run.log

  UVM_ERROR @  43805964 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  43805964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_test_vectors_sha3_224 has 1 failures.

16.kmac_test_vectors_sha3_224.40198380083580090784028395087431928749489143118955267282206916684235675431587
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/16.kmac_test_vectors_sha3_224/latest/run.log

  UVM_ERROR @  84564210 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  84564210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_test_vectors_sha3_384 has 1 failures.

25.kmac_test_vectors_sha3_384.22460278343927685916830099494277352470061858010417903014600602447712103857015
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/25.kmac_test_vectors_sha3_384/latest/run.log

  UVM_ERROR @  47499075 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  47499075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_smoke has 1 failures.

30.kmac_smoke.46057214614089276539547597034512083351279393769307033744671434329340469515043
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/30.kmac_smoke/latest/run.log

  UVM_ERROR @  56889771 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  56889771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 2 failures:
- Test kmac_stress_all_with_rand_reset has 2 failures.
  - 2.kmac_stress_all_with_rand_reset.36363322772961593956466861285476395180094192881767779809932089832454342572193
    Line 263, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  33425837 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483664 [0x80000010]) reg name: kmac_reg_block.err_code
  UVM_INFO @  33425837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.kmac_stress_all_with_rand_reset.93862472426593954524498592454807584205245287500694587149502737382089632267647
    Line 1286, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 65060250853 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483664 [0x80000010]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 65060250853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_*.prefix_* reset value: * has 1 failures:
- Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.
  - 2.kmac_shadow_reg_errors_with_csr_rw.112830059695411664841851711063859545226680860518450727223560056024078504959713
    Line 255, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @  18278862 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (2399925873 [0x8f0bf671] vs 2951066375 [0xafe5b307]) Regname: kmac_reg_block.prefix_4.prefix_0 reset value: 0x0
  UVM_INFO @  18278862 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 1 failures:
- Test kmac_stress_all has 1 failures.
  - 9.kmac_stress_all.79266715136068773799710376398471264658143072896636674997714437578836153615154
    Line 1236, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 62471703353 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 62471703353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_entropy_refresh has 1 failures.
  - 32.kmac_entropy_refresh.49753927908197565952077715942920473304533048640727908629522897696459167143145
    Line 853, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/32.kmac_entropy_refresh/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```