KMAC/MASKED Simulation Results

Friday July 19 2024 23:02:26 UTC

GitHub Revision: `e971cd9798`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 26138077499038500271813583950138268511494909685260487774440110801232111361107

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.456m	4.171ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.110s	132.137us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.200s	502.441us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	21.560s	2.840ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	7.870s	133.738us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.740s	411.688us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.200s	502.441us	20	20	100.00
		kmac_csr_aliasing	7.870s	133.738us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.770s	116.143us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.430s	41.751us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	53.173m	191.464ms	50	50	100.00
V2	burst_write	kmac_burst_write	25.688m	31.814ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	43.930m	464.047ms	50	50	100.00
		kmac_test_vectors_sha3_256	42.013m	574.747ms	50	50	100.00
		kmac_test_vectors_sha3_384	31.671m	290.834ms	50	50	100.00
		kmac_test_vectors_sha3_512	24.841m	270.235ms	50	50	100.00
		kmac_test_vectors_shake_128	1.800h	557.783ms	50	50	100.00
		kmac_test_vectors_shake_256	1.558h	497.565ms	50	50	100.00
		kmac_test_vectors_kmac	7.260s	1.119ms	50	50	100.00
		kmac_test_vectors_kmac_xof	7.270s	279.427us	50	50	100.00
V2	sideload	kmac_sideload	10.556m	253.708ms	50	50	100.00
V2	app	kmac_app	7.116m	73.317ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.300m	5.743ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	7.642m	19.846ms	48	50	96.00
V2	error	kmac_error	8.659m	200.000ms	48	50	96.00
V2	key_error	kmac_key_error	13.590s	20.607ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	50.200s	2.110ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	38.200s	1.411ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.003m	4.481ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	50.960s	969.598us	50	50	100.00
V2	stress_all	kmac_stress_all	53.685m	31.018ms	48	50	96.00
V2	intr_test	kmac_intr_test	0.880s	24.556us	50	50	100.00
V2	alert_test	kmac_alert_test	1.010s	253.726us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.440s	55.495us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.440s	55.495us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.110s	132.137us	5	5	100.00
		kmac_csr_rw	1.200s	502.441us	20	20	100.00
		kmac_csr_aliasing	7.870s	133.738us	5	5	100.00
		kmac_same_csr_outstanding	2.750s	462.792us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.110s	132.137us	5	5	100.00
		kmac_csr_rw	1.200s	502.441us	20	20	100.00
		kmac_csr_aliasing	7.870s	133.738us	5	5	100.00
		kmac_same_csr_outstanding	2.750s	462.792us	20	20	100.00
V2		TOTAL			1043	1050	99.33
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.470s	141.770us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.470s	141.770us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.470s	141.770us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.470s	141.770us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.080s	424.248us	19	20	95.00
V2S	tl_intg_err	kmac_sec_cm	2.165m	112.781ms	5	5	100.00
		kmac_tl_intg_err	5.370s	411.676us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.370s	411.676us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	50.960s	969.598us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.456m	4.171ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	10.556m	253.708ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.470s	141.770us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	2.165m	112.781ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	2.165m	112.781ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	2.165m	112.781ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.456m	4.171ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	50.960s	969.598us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	2.165m	112.781ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.307m	33.234ms	9	10	90.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.456m	4.171ms	50	50	100.00
V2S		TOTAL			73	75	97.33
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	37.621m	434.451ms	5	10	50.00
V3		TOTAL			5	10	50.00
		TOTAL			1236	1250	98.88

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	21	84.00
V2S	5	5	3	60.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.45	97.91	92.65	99.89	78.17	95.59	99.05	97.88

Failure Buckets

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 4 failures:

Test kmac_mubi has 1 failures.

0.kmac_mubi.20701256508513432149559800955539112685993411318439433748779213243096780361944
Line 587, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_mubi/latest/run.log

  UVM_FATAL @ 2062443165 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (161 [0xa1] vs 181 [0xb5]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 2062443165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 1 failures.

6.kmac_entropy_refresh.96103112386583105851520643916150499492765191679587034522235885018567435148150
Line 431, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 7163493953 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (106 [0x6a] vs 98 [0x62]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 7163493953 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_error has 1 failures.

23.kmac_error.37146473066142846896386486482764950358957638715924787761796343839927754516915
Line 614, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/23.kmac_error/latest/run.log

  UVM_FATAL @ 81156639613 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (111 [0x6f] vs 172 [0xac]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 81156639613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 1 failures.

25.kmac_stress_all.62442352531156760811793724851708644658465665397696041104492088026730970346417
Line 1313, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/25.kmac_stress_all/latest/run.log

  UVM_FATAL @ 99840894034 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (134 [0x86] vs 213 [0xd5]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 99840894034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:839) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 4 failures:
- Test kmac_stress_all_with_rand_reset has 4 failures.
  - 0.kmac_stress_all_with_rand_reset.93489003154712102393282220318348178288254277972185415179105867779974748454168
    Line 1390, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 164014114258 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 164014114258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.kmac_stress_all_with_rand_reset.110101459130643635425363202752072755150748287722764286728321295623668096883807
    Line 439, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5817756081 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 5817756081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test kmac_burst_write has 1 failures.
  - 29.kmac_burst_write.2666835501167696933149740812218127171970660440436259430796382101012183378094
    Line 824, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/29.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_error has 1 failures.
  - 41.kmac_error.108337421604774337502914164284750364549316895741281707481731149135994499728312
    Line 1170, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/41.kmac_error/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_* reset value: * has 1 failures:
- Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.
  - 0.kmac_shadow_reg_errors_with_csr_rw.36853127609376079282185254258734481647854585761378905332180154646069323011765
    Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @   4775839 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1406656221 [0x53d7dedd] vs 0 [0x0]) Regname: kmac_reg_block.prefix_4 reset value: 0x0
  UVM_INFO @   4775839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 6.kmac_stress_all_with_rand_reset.63752848367974409620985011241503137357844849975814070686096534003493343774901
    Line 553, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2428366092 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483752 [0x80000068]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 2428366092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 1 failures:
- Test kmac_entropy_refresh has 1 failures.
  - 17.kmac_entropy_refresh.13393246422783920882139928658649277338176965106169789365100358432436505521444
    Line 502, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/17.kmac_entropy_refresh/latest/run.log
```
  UVM_ERROR @ 7382272662 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 7382272662 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 1 failures:
- Test kmac_stress_all has 1 failures.
  - 23.kmac_stress_all.108826326832921884344140431629306637050510807173090018981501634594423450733098
    Line 1140, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/23.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 195522037972 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 195522037972 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```