KMAC/MASKED Simulation Results

Monday July 22 2024 23:02:17 UTC

GitHub Revision: `3e0219a2c5`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 78193674045195286552709223969981662100934453993551616519215297815848091296886

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.584m	16.595ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.160s	108.899us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.190s	26.216us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	22.320s	7.561ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	7.900s	998.475us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.790s	356.261us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.190s	26.216us	20	20	100.00
		kmac_csr_aliasing	7.900s	998.475us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.820s	109.397us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.480s	68.462us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	52.575m	119.030ms	50	50	100.00
V2	burst_write	kmac_burst_write	25.408m	57.829ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	44.399m	1.216s	50	50	100.00
		kmac_test_vectors_sha3_256	37.871m	94.258ms	50	50	100.00
		kmac_test_vectors_sha3_384	35.459m	1.147s	48	50	96.00
		kmac_test_vectors_sha3_512	23.627m	814.643ms	49	50	98.00
		kmac_test_vectors_shake_128	1.929h	3.725s	49	50	98.00
		kmac_test_vectors_shake_256	1.660h	3.658s	50	50	100.00
		kmac_test_vectors_kmac	7.430s	617.419us	49	50	98.00
		kmac_test_vectors_kmac_xof	7.100s	1.476ms	50	50	100.00
V2	sideload	kmac_sideload	9.079m	221.174ms	50	50	100.00
V2	app	kmac_app	7.292m	29.089ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.284m	8.866ms	9	10	90.00
V2	entropy_refresh	kmac_entropy_refresh	7.118m	172.045ms	48	50	96.00
V2	error	kmac_error	8.635m	5.699ms	50	50	100.00
V2	key_error	kmac_key_error	21.990s	21.883ms	49	50	98.00
V2	edn_timeout_error	kmac_edn_timeout_error	38.370s	1.700ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	46.220s	12.525ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.192m	7.374ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	27.250s	2.012ms	50	50	100.00
V2	stress_all	kmac_stress_all	42.848m	108.192ms	47	50	94.00
V2	intr_test	kmac_intr_test	0.900s	18.622us	50	50	100.00
V2	alert_test	kmac_alert_test	0.940s	55.415us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.580s	144.118us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.580s	144.118us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.160s	108.899us	5	5	100.00
		kmac_csr_rw	1.190s	26.216us	20	20	100.00
		kmac_csr_aliasing	7.900s	998.475us	5	5	100.00
		kmac_same_csr_outstanding	2.600s	555.684us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.160s	108.899us	5	5	100.00
		kmac_csr_rw	1.190s	26.216us	20	20	100.00
		kmac_csr_aliasing	7.900s	998.475us	5	5	100.00
		kmac_same_csr_outstanding	2.600s	555.684us	20	20	100.00
V2		TOTAL			1038	1050	98.86
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.590s	139.672us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.590s	139.672us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.590s	139.672us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.590s	139.672us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.050s	921.191us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.675m	24.803ms	5	5	100.00
		kmac_tl_intg_err	5.670s	498.353us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.670s	498.353us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	27.250s	2.012ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.584m	16.595ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	9.079m	221.174ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.590s	139.672us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.675m	24.803ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.675m	24.803ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.675m	24.803ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.584m	16.595ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	27.250s	2.012ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.675m	24.803ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.316m	67.485ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.584m	16.595ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	39.489m	62.315ms	4	10	40.00
V3		TOTAL			4	10	40.00
		TOTAL			1232	1250	98.56

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	17	68.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.20	97.89	92.55	99.89	76.76	95.53	98.89	97.88

Failure Buckets

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 6 failures:

Test kmac_test_vectors_shake_128 has 1 failures.

1.kmac_test_vectors_shake_128.12808596899652158029052612250151916860844126572358563709168461722068820899060
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_test_vectors_shake_128/latest/run.log

  UVM_ERROR @  46525895 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  46525895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_test_vectors_kmac has 1 failures.

3.kmac_test_vectors_kmac.58361847030453377697635276272687987664963378772002648328067527887273783322470
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_test_vectors_kmac/latest/run.log

  UVM_ERROR @ 102646946 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 102646946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_test_vectors_sha3_384 has 2 failures.

8.kmac_test_vectors_sha3_384.61590881675858228096666934864821123033547964505268539370173645517056112092844
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_test_vectors_sha3_384/latest/run.log

  UVM_ERROR @  22277570 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  22277570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

42.kmac_test_vectors_sha3_384.81353024107769182919489238637939501015967678360056533774907018077359712134381
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/42.kmac_test_vectors_sha3_384/latest/run.log

  UVM_ERROR @ 129037057 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 129037057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 1 failures.

15.kmac_stress_all.43664362370015069626159878665852386370693604196531628063185130827781232422949
Line 954, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/15.kmac_stress_all/latest/run.log

  UVM_ERROR @ 21153165725 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 21153165725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_test_vectors_sha3_512 has 1 failures.

39.kmac_test_vectors_sha3_512.99058439263470290043161854201770309004172915380556179604737008502091725398557
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/39.kmac_test_vectors_sha3_512/latest/run.log

  UVM_ERROR @  78064718 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  78064718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:839) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 5 failures:
- Test kmac_stress_all_with_rand_reset has 5 failures.
  - 3.kmac_stress_all_with_rand_reset.27963410919651115908925337034199231015888925264601094306442928083114811779005
    Line 328, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 21836424634 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 21836424634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.kmac_stress_all_with_rand_reset.114611847794695702651718087846909798879876224838632150918022635348822561877893
    Line 379, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10039428604 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 10039428604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test kmac_app_with_partial_data has 1 failures.
  - 0.kmac_app_with_partial_data.52281963121538683771952162899950725702734641433443720153896421856417365954255
    Line 907, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_app_with_partial_data/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_entropy_refresh has 1 failures.
  - 30.kmac_entropy_refresh.76524996644430775205546180563055800258075430762606232081624749801623199008709
    Line 1064, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/30.kmac_entropy_refresh/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 2 failures:
- Test kmac_stress_all has 1 failures.
  - 10.kmac_stress_all.77212256959879461652296825076177514827974467089388491831536105385925764792687
    Line 493, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/10.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 3181411662 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (77 [0x4d] vs 70 [0x46]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 3181411662 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_entropy_refresh has 1 failures.
  - 33.kmac_entropy_refresh.58116413644546021851730667741213296681341510344605400587413654446850405860720
    Line 895, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/33.kmac_entropy_refresh/latest/run.log
```
  UVM_FATAL @ 10540342377 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (5 [0x5] vs 241 [0xf1]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 10540342377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 6.kmac_stress_all_with_rand_reset.10610766792153063883426968042480004877181092067268569204973318647779864549414
    Line 1246, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 153549667497 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483760 [0x80000070]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 153549667497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 1 failures:
- Test kmac_stress_all has 1 failures.
  - 8.kmac_stress_all.6256573864285784031344023655758242603751219186310978961618299040535021241759
    Line 980, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 13443919565 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 13443919565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.err_code reset value: * has 1 failures:
- Test kmac_key_error has 1 failures.
  - 21.kmac_key_error.107510983328867893269830723198865777970317797054833222606018954773343871295599
    Line 251, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/21.kmac_key_error/latest/run.log
```
  UVM_ERROR @ 271360073 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 16777216 [0x1000000]) Regname: kmac_reg_block.err_code reset value: 0x0
  UVM_INFO @ 271360073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```