KMAC/MASKED Simulation Results

Tuesday July 23 2024 23:02:17 UTC

GitHub Revision: `0bfa990ddc`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 18885947517810151702135064218189465175127531856323617115052940021793720055953

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.448m	12.435ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.200s	127.123us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.220s	55.702us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	23.070s	1.495ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.120s	395.065us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.670s	152.117us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.220s	55.702us	20	20	100.00
		kmac_csr_aliasing	9.120s	395.065us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.810s	15.549us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.350s	54.541us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	57.640m	130.293ms	50	50	100.00
V2	burst_write	kmac_burst_write	26.639m	61.573ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	45.836m	991.961ms	50	50	100.00
		kmac_test_vectors_sha3_256	41.249m	1.032s	50	50	100.00
		kmac_test_vectors_sha3_384	32.438m	610.389ms	49	50	98.00
		kmac_test_vectors_sha3_512	24.225m	384.614ms	50	50	100.00
		kmac_test_vectors_shake_128	1.907h	2.867s	50	50	100.00
		kmac_test_vectors_shake_256	1.582h	1.159s	50	50	100.00
		kmac_test_vectors_kmac	7.270s	1.158ms	50	50	100.00
		kmac_test_vectors_kmac_xof	7.360s	214.931us	50	50	100.00
V2	sideload	kmac_sideload	8.400m	19.664ms	50	50	100.00
V2	app	kmac_app	6.616m	59.820ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	3.954m	9.002ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	7.462m	79.790ms	49	50	98.00
V2	error	kmac_error	8.420m	5.189ms	48	50	96.00
V2	key_error	kmac_key_error	14.010s	2.998ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	51.730s	2.595ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	44.530s	654.657us	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.024m	27.760ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	23.640s	746.625us	50	50	100.00
V2	stress_all	kmac_stress_all	1.132h	151.394ms	48	50	96.00
V2	intr_test	kmac_intr_test	0.880s	13.715us	50	50	100.00
V2	alert_test	kmac_alert_test	0.970s	96.561us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.440s	193.126us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.440s	193.126us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.200s	127.123us	5	5	100.00
		kmac_csr_rw	1.220s	55.702us	20	20	100.00
		kmac_csr_aliasing	9.120s	395.065us	5	5	100.00
		kmac_same_csr_outstanding	2.810s	1.570ms	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.200s	127.123us	5	5	100.00
		kmac_csr_rw	1.220s	55.702us	20	20	100.00
		kmac_csr_aliasing	9.120s	395.065us	5	5	100.00
		kmac_same_csr_outstanding	2.810s	1.570ms	20	20	100.00
V2		TOTAL			1043	1050	99.33
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.600s	112.921us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.600s	112.921us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.600s	112.921us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.600s	112.921us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.050s	264.737us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.718m	7.471ms	5	5	100.00
		kmac_tl_intg_err	6.240s	3.745ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	6.240s	3.745ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	23.640s	746.625us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.448m	12.435ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	8.400m	19.664ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.600s	112.921us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.718m	7.471ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.718m	7.471ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.718m	7.471ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.448m	12.435ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	23.640s	746.625us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.718m	7.471ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.534m	17.607ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.448m	12.435ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	27.019m	223.977ms	4	10	40.00
V3		TOTAL			4	10	40.00
		TOTAL			1237	1250	98.96

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	20	80.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.30	97.89	92.55	99.89	77.46	95.53	98.89	97.88

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:839) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 5 failures:
- Test kmac_stress_all_with_rand_reset has 5 failures.
  - 0.kmac_stress_all_with_rand_reset.60818490555587085138633725510185902304926653473277190722395522264431352015853
    Line 478, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6404816175 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 6404816175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.kmac_stress_all_with_rand_reset.53993949795764961308428824359380090349422921409309637338323839640066137241383
    Line 258, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 555600102 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 555600102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 3 failures:
- Test kmac_stress_all has 2 failures.
  - 2.kmac_stress_all.91596445325992265180039267447242607083356321240160141427341612486808834701890
    Line 1771, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 105524951342 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 105524951342 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 35.kmac_stress_all.73109141141993564994874376737227759129782690118091958475843700619100206227413
    Line 542, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/35.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 12786310624 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 12786310624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_error has 1 failures.
  - 12.kmac_error.110307198602455305528103156780748856724855605389214588027609802536157872445161
    Line 769, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/12.kmac_error/latest/run.log
```
  UVM_FATAL @ 10010738406 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 10010738406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 2 failures:
- Test kmac_app has 1 failures.
  - 13.kmac_app.112940145175624720178964137519430220078074761992046923318595106021220854884088
    Line 379, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/13.kmac_app/latest/run.log
```
  UVM_FATAL @ 1580527430 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (214 [0xd6] vs 190 [0xbe]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 1580527430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_entropy_refresh has 1 failures.
  - 33.kmac_entropy_refresh.9887488837947563374916810082128966176946121461678846546096066962389864113675
    Line 391, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/33.kmac_entropy_refresh/latest/run.log
```
  UVM_FATAL @ 20630950358 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (122 [0x7a] vs 171 [0xab]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 20630950358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 2 failures:
- Test kmac_test_vectors_sha3_384 has 1 failures.
  - 23.kmac_test_vectors_sha3_384.38803224509002628133676297991963588425516461022566806650617025748890166329792
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/23.kmac_test_vectors_sha3_384/latest/run.log
```
  UVM_ERROR @  60959063 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  60959063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_error has 1 failures.
  - 33.kmac_error.59412881840346225456624483671208439639145894726433314492030440160717003889990
    Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/33.kmac_error/latest/run.log
```
  UVM_ERROR @  45736063 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  45736063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 7.kmac_stress_all_with_rand_reset.110948618106185553912510366944708117446336052030920677013412453521007506020432
    Line 302, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5744009248 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483704 [0x80000038]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 5744009248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

KMAC/MASKED Simulation Results

Tuesday July 23 2024 23:02:17 UTC

GitHub Revision: 0bfa990ddc

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 18885947517810151702135064218189465175127531856323617115052940021793720055953

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `0bfa990ddc`