KMAC/MASKED Simulation Results

Wednesday July 24 2024 23:04:46 UTC

GitHub Revision: `e439226b6c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 80778109121175195808319778278610424989650974127729484509360263424111433728567

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.572m	10.735ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.270s	195.553us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.220s	35.420us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	20.800s	1.686ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.720s	398.089us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.630s	305.621us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.220s	35.420us	20	20	100.00
		kmac_csr_aliasing	9.720s	398.089us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.800s	37.293us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.440s	154.185us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	57.535m	97.368ms	50	50	100.00
V2	burst_write	kmac_burst_write	29.835m	61.776ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	43.270m	257.986ms	49	50	98.00
		kmac_test_vectors_sha3_256	41.194m	185.458ms	50	50	100.00
		kmac_test_vectors_sha3_384	30.849m	47.245ms	46	50	92.00
		kmac_test_vectors_sha3_512	24.430m	102.330ms	50	50	100.00
		kmac_test_vectors_shake_128	1.809h	1.081s	49	50	98.00
		kmac_test_vectors_shake_256	1.530h	1.079s	50	50	100.00
		kmac_test_vectors_kmac	7.030s	2.322ms	50	50	100.00
		kmac_test_vectors_kmac_xof	7.540s	261.141us	50	50	100.00
V2	sideload	kmac_sideload	8.910m	211.033ms	50	50	100.00
V2	app	kmac_app	6.887m	25.337ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.166m	9.204ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	7.255m	20.569ms	50	50	100.00
V2	error	kmac_error	9.013m	85.431ms	50	50	100.00
V2	key_error	kmac_key_error	16.610s	10.727ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	1.003m	7.051ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	21.740s	529.941us	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.315m	6.939ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	48.580s	1.666ms	50	50	100.00
V2	stress_all	kmac_stress_all	50.264m	651.099ms	45	50	90.00
V2	intr_test	kmac_intr_test	0.910s	14.514us	50	50	100.00
V2	alert_test	kmac_alert_test	0.900s	16.676us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.620s	153.100us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.620s	153.100us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.270s	195.553us	5	5	100.00
		kmac_csr_rw	1.220s	35.420us	20	20	100.00
		kmac_csr_aliasing	9.720s	398.089us	5	5	100.00
		kmac_same_csr_outstanding	2.610s	177.075us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.270s	195.553us	5	5	100.00
		kmac_csr_rw	1.220s	35.420us	20	20	100.00
		kmac_csr_aliasing	9.720s	398.089us	5	5	100.00
		kmac_same_csr_outstanding	2.610s	177.075us	20	20	100.00
V2		TOTAL			1039	1050	98.95
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.470s	31.858us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.470s	31.858us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.470s	31.858us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.470s	31.858us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.100s	660.681us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	2.205m	19.681ms	5	5	100.00
		kmac_tl_intg_err	5.350s	251.994us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.350s	251.994us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	48.580s	1.666ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.572m	10.735ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	8.910m	211.033ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.470s	31.858us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	2.205m	19.681ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	2.205m	19.681ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	2.205m	19.681ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.572m	10.735ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	48.580s	1.666ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	2.205m	19.681ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.918m	14.030ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.572m	10.735ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	34.630m	1.025s	3	10	30.00
V3		TOTAL			3	10	30.00
		TOTAL			1232	1250	98.56

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	21	84.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.35	97.91	92.65	99.89	77.46	95.59	99.05	97.88

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:839) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 5 failures:
- Test kmac_stress_all_with_rand_reset has 5 failures.
  - 1.kmac_stress_all_with_rand_reset.21229176571505504901019807330618746618154661489626665202609245096076726045480
    Line 295, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 48858740251 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 48858740251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.kmac_stress_all_with_rand_reset.23415479974502491410808960970886591904327192384650448910400233674151369587911
    Line 468, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 16915966792 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 16915966792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 5 failures:
- Test kmac_test_vectors_sha3_384 has 4 failures.
  - 20.kmac_test_vectors_sha3_384.45034016789649899624480314382934892135730177359278464410114616134248626007930
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/20.kmac_test_vectors_sha3_384/latest/run.log
```
  UVM_ERROR @ 110453666 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 110453666 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 22.kmac_test_vectors_sha3_384.61059560880410164053776223404645899081746702528875073732443538604757185916204
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/22.kmac_test_vectors_sha3_384/latest/run.log
```
  UVM_ERROR @ 139556204 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 139556204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
- Test kmac_test_vectors_sha3_224 has 1 failures.
  - 37.kmac_test_vectors_sha3_224.110265701829295315060118787786339236185140755567944412072652805521533388646935
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/37.kmac_test_vectors_sha3_224/latest/run.log
```
  UVM_ERROR @  23252340 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  23252340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 3 failures:
- Test kmac_stress_all has 3 failures.
  - 8.kmac_stress_all.2035844665558706331627269906253330044409320134033954412372197719028490550378
    Line 608, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 16834728193 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 16834728193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 24.kmac_stress_all.63566802196354357845101832695634165986197421942011798126078313455675655693446
    Line 922, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/24.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 257540417774 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 257540417774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 2 failures:
- Test kmac_stress_all_with_rand_reset has 2 failures.
  - 0.kmac_stress_all_with_rand_reset.1420422537998834030661241187197937418834198402462652045635665243502040130804
    Line 557, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 36694472949 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483768 [0x80000078]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 36694472949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.kmac_stress_all_with_rand_reset.23355609596847483825053319817508734061440449966108215933061429862762157517112
    Line 605, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 47244199714 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483656 [0x80000008]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 47244199714 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 2 failures:

Test kmac_stress_all has 2 failures.

5.kmac_stress_all.2447096572311464274136347881160618217459695656502788640074497026565930174090
Line 1067, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_stress_all/latest/run.log

  UVM_FATAL @ 43604595025 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (38 [0x26] vs 32 [0x20]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 43604595025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

49.kmac_stress_all.110746297325361101845150197206155875113695793761987794780000483325596597226322
Line 719, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/49.kmac_stress_all/latest/run.log

  UVM_FATAL @ 42901569862 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (63 [0x3f] vs 113 [0x71]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 42901569862 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_test_vectors_shake_128 has 1 failures.
  - 15.kmac_test_vectors_shake_128.73106059015319856518486903022343461365903390011069819225633231331176546699010
    Line 5069, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/15.kmac_test_vectors_shake_128/latest/run.log
```
  UVM_FATAL @ 5000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 5000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 5000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```