d09e282b26| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | kmac_smoke | 1.682m | 11.439ms | 49 | 50 | 98.00 |
| V1 | csr_hw_reset | kmac_csr_hw_reset | 1.170s | 297.378us | 5 | 5 | 100.00 |
| V1 | csr_rw | kmac_csr_rw | 1.170s | 48.282us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | kmac_csr_bit_bash | 19.870s | 3.854ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | kmac_csr_aliasing | 10.080s | 637.366us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | kmac_csr_mem_rw_with_rand_reset | 2.650s | 71.350us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | kmac_csr_rw | 1.170s | 48.282us | 20 | 20 | 100.00 |
| kmac_csr_aliasing | 10.080s | 637.366us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | kmac_mem_walk | 0.780s | 12.535us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | kmac_mem_partial_access | 1.510s | 33.067us | 5 | 5 | 100.00 |
| V1 | TOTAL | 114 | 115 | 99.13 | |||
| V2 | long_msg_and_output | kmac_long_msg_and_output | 1.494h | 324.447ms | 45 | 50 | 90.00 |
| V2 | burst_write | kmac_burst_write | 25.271m | 66.065ms | 50 | 50 | 100.00 |
| V2 | test_vectors | kmac_test_vectors_sha3_224 | 35.890m | 176.165ms | 5 | 5 | 100.00 |
| kmac_test_vectors_sha3_256 | 1.065h | 798.108ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_sha3_384 | 35.406m | 183.791ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_sha3_512 | 19.416m | 9.866ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_shake_128 | 1.165h | 75.235ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_shake_256 | 50.045m | 60.239ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_kmac | 3.280s | 458.280us | 5 | 5 | 100.00 | ||
| kmac_test_vectors_kmac_xof | 3.120s | 89.972us | 5 | 5 | 100.00 | ||
| V2 | sideload | kmac_sideload | 11.752m | 176.586ms | 50 | 50 | 100.00 |
| V2 | app | kmac_app | 6.850m | 30.191ms | 50 | 50 | 100.00 |
| V2 | app_with_partial_data | kmac_app_with_partial_data | 7.127m | 20.373ms | 10 | 10 | 100.00 |
| V2 | entropy_refresh | kmac_entropy_refresh | 6.996m | 18.545ms | 50 | 50 | 100.00 |
| V2 | error | kmac_error | 8.725m | 63.671ms | 49 | 50 | 98.00 |
| V2 | key_error | kmac_key_error | 16.670s | 17.702ms | 50 | 50 | 100.00 |
| V2 | edn_timeout_error | kmac_edn_timeout_error | 50.000s | 1.195ms | 20 | 20 | 100.00 |
| V2 | entropy_mode_error | kmac_entropy_mode_error | 24.090s | 2.923ms | 20 | 20 | 100.00 |
| V2 | entropy_ready_error | kmac_entropy_ready_error | 1.111m | 5.870ms | 10 | 10 | 100.00 |
| V2 | lc_escalation | kmac_lc_escalation | 30.390s | 3.093ms | 49 | 50 | 98.00 |
| V2 | stress_all | kmac_stress_all | 1.353h | 527.947ms | 49 | 50 | 98.00 |
| V2 | intr_test | kmac_intr_test | 0.880s | 50.771us | 50 | 50 | 100.00 |
| V2 | alert_test | kmac_alert_test | 0.960s | 23.916us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | kmac_tl_errors | 4.260s | 178.450us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | kmac_tl_errors | 4.260s | 178.450us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | kmac_csr_hw_reset | 1.170s | 297.378us | 5 | 5 | 100.00 |
| kmac_csr_rw | 1.170s | 48.282us | 20 | 20 | 100.00 | ||
| kmac_csr_aliasing | 10.080s | 637.366us | 5 | 5 | 100.00 | ||
| kmac_same_csr_outstanding | 2.620s | 1.027ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | kmac_csr_hw_reset | 1.170s | 297.378us | 5 | 5 | 100.00 |
| kmac_csr_rw | 1.170s | 48.282us | 20 | 20 | 100.00 | ||
| kmac_csr_aliasing | 10.080s | 637.366us | 5 | 5 | 100.00 | ||
| kmac_same_csr_outstanding | 2.620s | 1.027ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 682 | 690 | 98.84 | |||
| V2S | shadow_reg_update_error | kmac_shadow_reg_errors | 1.640s | 160.157us | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | kmac_shadow_reg_errors | 1.640s | 160.157us | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | kmac_shadow_reg_errors | 1.640s | 160.157us | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | kmac_shadow_reg_errors | 1.640s | 160.157us | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | kmac_shadow_reg_errors_with_csr_rw | 3.050s | 137.112us | 20 | 20 | 100.00 |
| V2S | tl_intg_err | kmac_sec_cm | 1.462m | 36.406ms | 5 | 5 | 100.00 |
| kmac_tl_intg_err | 5.140s | 352.597us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | kmac_tl_intg_err | 5.140s | 352.597us | 20 | 20 | 100.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | kmac_lc_escalation | 30.390s | 3.093ms | 49 | 50 | 98.00 |
| V2S | sec_cm_sw_key_key_masking | kmac_smoke | 1.682m | 11.439ms | 49 | 50 | 98.00 |
| V2S | sec_cm_key_sideload | kmac_sideload | 11.752m | 176.586ms | 50 | 50 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_shadow | kmac_shadow_reg_errors | 1.640s | 160.157us | 20 | 20 | 100.00 |
| V2S | sec_cm_fsm_sparse | kmac_sec_cm | 1.462m | 36.406ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ctr_redun | kmac_sec_cm | 1.462m | 36.406ms | 5 | 5 | 100.00 |
| V2S | sec_cm_packer_ctr_redun | kmac_sec_cm | 1.462m | 36.406ms | 5 | 5 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_regwen | kmac_smoke | 1.682m | 11.439ms | 49 | 50 | 98.00 |
| V2S | sec_cm_fsm_global_esc | kmac_lc_escalation | 30.390s | 3.093ms | 49 | 50 | 98.00 |
| V2S | sec_cm_fsm_local_esc | kmac_sec_cm | 1.462m | 36.406ms | 5 | 5 | 100.00 |
| V2S | sec_cm_absorbed_ctrl_mubi | kmac_mubi | 5.019m | 4.562ms | 9 | 10 | 90.00 |
| V2S | sec_cm_sw_cmd_ctrl_sparse | kmac_smoke | 1.682m | 11.439ms | 49 | 50 | 98.00 |
| V2S | TOTAL | 74 | 75 | 98.67 | |||
| V3 | throughput | kmac_throughput | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | kmac_stress_all_with_rand_reset | 4.169m | 14.884ms | 0 | 10 | 0.00 |
| V3 | TOTAL | 0 | 10 | 0.00 | |||
| TOTAL | 870 | 890 | 97.75 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 25 | 25 | 21 | 84.00 |
| V2S | 5 | 5 | 4 | 80.00 |
| V3 | 2 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 93.79 | 97.80 | 91.00 | 99.89 | 76.06 | 95.17 | 98.89 | 97.73 |
UVM_ERROR (kmac_scoreboard.sv:1188) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 6 failures:
0.kmac_stress_all_with_rand_reset.77996277749821370587382153172383501570022989246098698441609826332440112455302
Line 297, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1328938335 ps: (kmac_scoreboard.sv:1188) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483648 [0x80000000]) reg name: kmac_reg_block.err_code
UVM_INFO @ 1328938335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.kmac_stress_all_with_rand_reset.70248948850831629478684233021907208089582877935512863176812513607868287809359
Line 263, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 642178976 ps: (kmac_scoreboard.sv:1188) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483680 [0x80000020]) reg name: kmac_reg_block.err_code
UVM_INFO @ 642178976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Job kmac_masked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 5 failures:
5.kmac_long_msg_and_output.54705799075931560301742175578885777062463858614383064950976022439175638379703
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_long_msg_and_output/latest/run.log
Job ID: smart:10eb8c6d-2df5-48aa-8331-feb2e72931bb
8.kmac_long_msg_and_output.6393197633435217662621622470070822984588784301405959770406254330941987376053
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_long_msg_and_output/latest/run.log
Job ID: smart:5c33d736-adf3-4f6b-991a-d537c43a7cee
... and 3 more failures.
UVM_ERROR (cip_base_vseq.sv:867) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 4 failures:
1.kmac_stress_all_with_rand_reset.99479360497088724855288739293198236924959293116693192553225793562246445416930
Line 291, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 878694797 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 878694797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.kmac_stress_all_with_rand_reset.12374628502005582878794389633174775652460559094611741708430851774713382208326
Line 299, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 555978947 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 555978947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (kmac_scoreboard.sv:1638) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 2 failures:
Test kmac_mubi has 1 failures.
1.kmac_mubi.26321972261619390572165190254262727463359742123469788505603737957621616409877
Line 565, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_mubi/latest/run.log
UVM_FATAL @ 3882091863 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (129 [0x81] vs 58 [0x3a]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 3882091863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_lc_escalation has 1 failures.
39.kmac_lc_escalation.94504545986508699264413590495873683850188054216789014494799797919182041380627
Line 276, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/39.kmac_lc_escalation/latest/run.log
UVM_FATAL @ 312500154 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (11 [0xb] vs 38 [0x26]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 312500154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 2 failures:
Test kmac_smoke has 1 failures.
14.kmac_smoke.108568756813917044908523068926821567231267836196392165380571600052825354838248
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_smoke/latest/run.log
UVM_ERROR @ 47322572 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 47322572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_stress_all has 1 failures.
45.kmac_stress_all.16828541096024304864760650933389871495283113093856448800830071004837384507760
Line 1822, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/45.kmac_stress_all/latest/run.log
UVM_ERROR @ 36385833911 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 36385833911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
47.kmac_error.58113793811650602708151009901500435063932331047552315859165235716524178613590
Line 1116, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/47.kmac_error/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---