KMAC/MASKED Simulation Results

Friday August 16 2024 23:02:10 UTC

GitHub Revision: `76588857da`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 107397868712693014844033025164446565408841343499325418676943424680076749785789

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.759m	9.611ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.130s	60.773us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.240s	61.042us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	20.010s	5.749ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	8.070s	286.884us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.530s	87.400us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.240s	61.042us	20	20	100.00
		kmac_csr_aliasing	8.070s	286.884us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.770s	35.072us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.550s	505.223us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	1.439h	348.445ms	40	50	80.00
V2	burst_write	kmac_burst_write	27.608m	35.138ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	1.030h	96.696ms	5	5	100.00
		kmac_test_vectors_sha3_256	1.017h	634.959ms	5	5	100.00
		kmac_test_vectors_sha3_384	33.252m	44.684ms	5	5	100.00
		kmac_test_vectors_sha3_512	28.758m	63.127ms	5	5	100.00
		kmac_test_vectors_shake_128	1.075h	503.904ms	5	5	100.00
		kmac_test_vectors_shake_256	36.434m	22.940ms	5	5	100.00
		kmac_test_vectors_kmac	3.350s	82.582us	4	5	80.00
		kmac_test_vectors_kmac_xof	3.110s	201.704us	5	5	100.00
V2	sideload	kmac_sideload	10.759m	98.855ms	50	50	100.00
V2	app	kmac_app	7.506m	16.829ms	47	50	94.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.029m	44.828ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	8.400m	112.552ms	50	50	100.00
V2	error	kmac_error	9.712m	15.513ms	50	50	100.00
V2	key_error	kmac_key_error	18.190s	17.094ms	49	50	98.00
V2	edn_timeout_error	kmac_edn_timeout_error	49.150s	631.571us	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	28.770s	2.131ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.076m	27.722ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	46.600s	860.091us	50	50	100.00
V2	stress_all	kmac_stress_all	1.091h	1.560s	49	50	98.00
V2	intr_test	kmac_intr_test	0.860s	18.083us	50	50	100.00
V2	alert_test	kmac_alert_test	0.920s	18.876us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.970s	61.639us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.970s	61.639us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.130s	60.773us	5	5	100.00
		kmac_csr_rw	1.240s	61.042us	20	20	100.00
		kmac_csr_aliasing	8.070s	286.884us	5	5	100.00
		kmac_same_csr_outstanding	2.850s	122.823us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.130s	60.773us	5	5	100.00
		kmac_csr_rw	1.240s	61.042us	20	20	100.00
		kmac_csr_aliasing	8.070s	286.884us	5	5	100.00
		kmac_same_csr_outstanding	2.850s	122.823us	20	20	100.00
V2		TOTAL			674	690	97.68
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.400s	47.953us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.400s	47.953us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.400s	47.953us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.400s	47.953us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.240s	733.769us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.430m	11.754ms	5	5	100.00
		kmac_tl_intg_err	5.750s	535.119us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.750s	535.119us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	46.600s	860.091us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.759m	9.611ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	10.759m	98.855ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.400s	47.953us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.430m	11.754ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.430m	11.754ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.430m	11.754ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.759m	9.611ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	46.600s	860.091us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.430m	11.754ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	7.030m	51.344ms	9	10	90.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.759m	9.611ms	50	50	100.00
V2S		TOTAL			74	75	98.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.488m	12.493ms	3	10	30.00
V3		TOTAL			3	10	30.00
		TOTAL			866	890	97.30

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	20	80.00
V2S	5	5	4	80.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.18	97.89	92.58	99.89	76.76	95.53	98.89	97.73

Failure Buckets

Job kmac_masked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 10 failures:
- Test kmac_long_msg_and_output has 10 failures.
  - 1.kmac_long_msg_and_output.23583235983730194767893111128843206090218175722215797629231945577329961634653
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:3dfed63d-ab1b-4e7a-8aca-ef1b97a4c681
```
  - 2.kmac_long_msg_and_output.115043996278122636504795100123895821992473831100480261653157932955373139773466
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:9f254bfe-0fac-4c3e-9a3d-932336161e23
```
  - ... and 8 more failures.
UVM_ERROR (cip_base_vseq.sv:867) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 4 failures:
- Test kmac_stress_all_with_rand_reset has 4 failures.
  - 4.kmac_stress_all_with_rand_reset.7631797140628161052341310331940475314275380426556977186891564624954758440951
    Line 344, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5508496088 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 5508496088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.kmac_stress_all_with_rand_reset.69511168013313057674586130713961423410503874305800778706651306733276198769592
    Line 327, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1548332139 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1548332139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

UVM_FATAL (kmac_scoreboard.sv:1638) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 4 failures:

Test kmac_stress_all has 1 failures.

6.kmac_stress_all.93477597245824303784151204982267271490296220882168436574524117403574976433393
Line 1215, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_stress_all/latest/run.log

  UVM_FATAL @ 40852637806 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (8 [0x8] vs 133 [0x85]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 40852637806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app has 3 failures.

10.kmac_app.38905960913952813138449691842296737674421349861934956166924627131488695170665
Line 973, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/10.kmac_app/latest/run.log

  UVM_FATAL @ 119718991651 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (128 [0x80] vs 81 [0x51]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 119718991651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

15.kmac_app.90021974168737496690758691868178493221013626421012718009666467652072394957631
Line 533, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/15.kmac_app/latest/run.log

  UVM_FATAL @ 4540409770 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (234 [0xea] vs 63 [0x3f]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 4540409770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (kmac_scoreboard.sv:1188) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 3 failures:
- Test kmac_stress_all_with_rand_reset has 3 failures.
  - 2.kmac_stress_all_with_rand_reset.74717450052708362400398744658670926622017968046385358083815780403468951626446
    Line 435, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 523012395 ps: (kmac_scoreboard.sv:1188) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483736 [0x80000058]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 523012395 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.kmac_stress_all_with_rand_reset.56701631331999257484682638900432363426707186744590517239529028697333500565923
    Line 396, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1360916899 ps: (kmac_scoreboard.sv:1188) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483712 [0x80000040]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 1360916899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_mubi has 1 failures.
  - 1.kmac_mubi.24778884117917829081423744586407813067193410144544571652417369234994749234741
    Line 1006, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_mubi/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (kmac_base_vseq.sv:382) [kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == *) intr_pins[KmacErr] is not set! has 1 failures:
- Test kmac_key_error has 1 failures.
  - 1.kmac_key_error.92259591602058950414142219963433890339289995230197419680124190338322944356650
    Line 279, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_key_error/latest/run.log
```
  UVM_ERROR @ 2755352229 ps: (kmac_base_vseq.sv:382) [uvm_test_top.env.virtual_sequencer.kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == 1) intr_pins[KmacErr] is not set!
  UVM_INFO @ 2755352229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 1 failures:
- Test kmac_test_vectors_kmac has 1 failures.
  - 4.kmac_test_vectors_kmac.12095208963949558918746027275965782276458005202607369166220051926581003217319
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_test_vectors_kmac/latest/run.log
```
  UVM_ERROR @  45080274 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  45080274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```