KMAC/MASKED Simulation Results

Saturday August 17 2024 23:02:17 UTC

GitHub Revision: `76588857da`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 94235727392619910305578226901221990521512464990339520078429467885466612377995

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.475m	21.579ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.190s	147.946us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.200s	67.298us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	19.810s	1.482ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.430s	2.751ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.850s	99.841us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.200s	67.298us	20	20	100.00
		kmac_csr_aliasing	9.430s	2.751ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.760s	10.561us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.550s	122.972us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	1.205h	335.981ms	45	50	90.00
V2	burst_write	kmac_burst_write	27.634m	158.145ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	58.352m	378.351ms	5	5	100.00
		kmac_test_vectors_sha3_256	47.745m	231.470ms	5	5	100.00
		kmac_test_vectors_sha3_384	40.153m	135.176ms	5	5	100.00
		kmac_test_vectors_sha3_512	20.766m	28.556ms	5	5	100.00
		kmac_test_vectors_shake_128	1.446h	2.127s	5	5	100.00
		kmac_test_vectors_shake_256	8.264m	28.817ms	5	5	100.00
		kmac_test_vectors_kmac	3.330s	397.225us	5	5	100.00
		kmac_test_vectors_kmac_xof	2.800s	46.489us	5	5	100.00
V2	sideload	kmac_sideload	9.253m	76.578ms	50	50	100.00
V2	app	kmac_app	6.814m	22.183ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	8.096m	241.901ms	9	10	90.00
V2	entropy_refresh	kmac_entropy_refresh	8.184m	75.480ms	48	50	96.00
V2	error	kmac_error	9.107m	57.219ms	50	50	100.00
V2	key_error	kmac_key_error	13.160s	8.608ms	49	50	98.00
V2	edn_timeout_error	kmac_edn_timeout_error	35.830s	560.010us	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	31.400s	6.756ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.058m	22.998ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	58.410s	1.070ms	50	50	100.00
V2	stress_all	kmac_stress_all	54.341m	85.651ms	50	50	100.00
V2	intr_test	kmac_intr_test	0.900s	144.128us	50	50	100.00
V2	alert_test	kmac_alert_test	0.960s	133.852us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.400s	55.038us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.400s	55.038us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.190s	147.946us	5	5	100.00
		kmac_csr_rw	1.200s	67.298us	20	20	100.00
		kmac_csr_aliasing	9.430s	2.751ms	5	5	100.00
		kmac_same_csr_outstanding	2.420s	91.513us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.190s	147.946us	5	5	100.00
		kmac_csr_rw	1.200s	67.298us	20	20	100.00
		kmac_csr_aliasing	9.430s	2.751ms	5	5	100.00
		kmac_same_csr_outstanding	2.420s	91.513us	20	20	100.00
V2		TOTAL			680	690	98.55
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.320s	136.395us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.320s	136.395us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.320s	136.395us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.320s	136.395us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.990s	394.332us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.810m	8.029ms	5	5	100.00
		kmac_tl_intg_err	5.450s	255.434us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.450s	255.434us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	58.410s	1.070ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.475m	21.579ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	9.253m	76.578ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.320s	136.395us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.810m	8.029ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.810m	8.029ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.810m	8.029ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.475m	21.579ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	58.410s	1.070ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.810m	8.029ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.961m	10.308ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.475m	21.579ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	2.141m	1.425ms	2	10	20.00
V3		TOTAL			2	10	20.00
		TOTAL			872	890	97.98

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	20	80.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.50	97.89	92.55	99.89	78.87	95.53	98.89	97.88

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 5 failures:
- Test kmac_stress_all_with_rand_reset has 5 failures.
  - 0.kmac_stress_all_with_rand_reset.64061991344644214622512600990965295157147942576514912209197220848165779731344
    Line 328, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 937020966 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 937020966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.kmac_stress_all_with_rand_reset.112621030164175015467896648266993521663460265770153454938188562602453811975692
    Line 410, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1164788955 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1164788955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
Job kmac_masked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 5 failures:
- Test kmac_long_msg_and_output has 5 failures.
  - 6.kmac_long_msg_and_output.69006062386444664674756977406080319057005465863681474688517450883842614062452
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:394ef749-4967-4046-9cea-676b70cc5037
```
  - 24.kmac_long_msg_and_output.63704667853901749245512056018553499871094680935344609964101421008880086278830
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/24.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:adaf4802-9b42-4820-a6b9-845f4e08fe61
```
  - ... and 3 more failures.
UVM_ERROR (kmac_scoreboard.sv:1188) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 3 failures:
- Test kmac_stress_all_with_rand_reset has 3 failures.
  - 1.kmac_stress_all_with_rand_reset.73476277354479941237074886740310012688541218182675344560937313848838919439412
    Line 262, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 165438734 ps: (kmac_scoreboard.sv:1188) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483672 [0x80000018]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 165438734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.kmac_stress_all_with_rand_reset.77535212895798411475493905029076751877915692501618823558029044335711543160653
    Line 262, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  32456213 ps: (kmac_scoreboard.sv:1188) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483712 [0x80000040]) reg name: kmac_reg_block.err_code
  UVM_INFO @  32456213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

UVM_FATAL (kmac_scoreboard.sv:1638) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 3 failures:

Test kmac_app_with_partial_data has 1 failures.

3.kmac_app_with_partial_data.75873528633794303856369990656385146287953695122378652406470245565882939914016
Line 277, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_app_with_partial_data/latest/run.log

  UVM_FATAL @ 414352353 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (0 [0x0] vs 131 [0x83]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 414352353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app has 1 failures.

34.kmac_app.42025101738855025767570343709145119647867503652902336842148277831856329625741
Line 449, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/34.kmac_app/latest/run.log

  UVM_FATAL @ 9350221331 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (203 [0xcb] vs 199 [0xc7]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 9350221331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 1 failures.

44.kmac_entropy_refresh.61971946767269700352062385536296681314237638790429062124885343594625329964229
Line 509, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/44.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 5743898454 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (178 [0xb2] vs 184 [0xb8]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 5743898454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 1 failures:
- Test kmac_entropy_refresh has 1 failures.
  - 23.kmac_entropy_refresh.88964327427575666090049777274271809692806645823903999770456996541364043720022
    Line 508, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/23.kmac_entropy_refresh/latest/run.log
```
  UVM_ERROR @ 6692369736 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 6692369736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (kmac_base_vseq.sv:382) [kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == *) intr_pins[KmacErr] is not set! has 1 failures:
- Test kmac_key_error has 1 failures.
  - 43.kmac_key_error.34651260660273393833408164665921969118084699115431509286130493083031704504148
    Line 255, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/43.kmac_key_error/latest/run.log
```
  UVM_ERROR @ 505413441 ps: (kmac_base_vseq.sv:382) [uvm_test_top.env.virtual_sequencer.kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == 1) intr_pins[KmacErr] is not set!
  UVM_INFO @ 505413441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```