KMAC/MASKED Simulation Results

Sunday August 18 2024 23:02:23 UTC

GitHub Revision: `f1535c5540`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 29514139809134543525249635699831421949407409612590789671953066019961489233719

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.831m	5.565ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.170s	39.232us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.180s	194.450us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	16.640s	577.897us	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.030s	3.824ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.780s	355.853us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.180s	194.450us	20	20	100.00
		kmac_csr_aliasing	10.030s	3.824ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.760s	29.744us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.610s	39.755us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	1.425h	446.333ms	44	50	88.00
V2	burst_write	kmac_burst_write	28.212m	61.884ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	57.183m	363.875ms	5	5	100.00
		kmac_test_vectors_sha3_256	57.901m	934.053ms	5	5	100.00
		kmac_test_vectors_sha3_384	37.336m	47.951ms	5	5	100.00
		kmac_test_vectors_sha3_512	26.354m	35.798ms	5	5	100.00
		kmac_test_vectors_shake_128	1.303h	111.809ms	5	5	100.00
		kmac_test_vectors_shake_256	8.142m	38.454ms	5	5	100.00
		kmac_test_vectors_kmac	3.200s	144.897us	5	5	100.00
		kmac_test_vectors_kmac_xof	3.950s	253.312us	5	5	100.00
V2	sideload	kmac_sideload	9.824m	20.230ms	50	50	100.00
V2	app	kmac_app	8.403m	80.139ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	7.562m	65.501ms	9	10	90.00
V2	entropy_refresh	kmac_entropy_refresh	8.098m	204.649ms	49	50	98.00
V2	error	kmac_error	10.755m	155.446ms	48	50	96.00
V2	key_error	kmac_key_error	12.260s	1.659ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	53.130s	4.083ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	27.480s	1.620ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.922m	123.929ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	55.890s	4.900ms	50	50	100.00
V2	stress_all	kmac_stress_all	1.039h	223.750ms	49	50	98.00
V2	intr_test	kmac_intr_test	0.900s	188.637us	50	50	100.00
V2	alert_test	kmac_alert_test	0.940s	166.795us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.000s	622.957us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.000s	622.957us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.170s	39.232us	5	5	100.00
		kmac_csr_rw	1.180s	194.450us	20	20	100.00
		kmac_csr_aliasing	10.030s	3.824ms	5	5	100.00
		kmac_same_csr_outstanding	2.750s	688.807us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.170s	39.232us	5	5	100.00
		kmac_csr_rw	1.180s	194.450us	20	20	100.00
		kmac_csr_aliasing	10.030s	3.824ms	5	5	100.00
		kmac_same_csr_outstanding	2.750s	688.807us	20	20	100.00
V2		TOTAL			678	690	98.26
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.620s	114.570us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.620s	114.570us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.620s	114.570us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.620s	114.570us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.050s	450.349us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.613m	11.267ms	5	5	100.00
		kmac_tl_intg_err	4.810s	672.149us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.810s	672.149us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	55.890s	4.900ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.831m	5.565ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	9.824m	20.230ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.620s	114.570us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.613m	11.267ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.613m	11.267ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.613m	11.267ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.831m	5.565ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	55.890s	4.900ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.613m	11.267ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.730m	84.369ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.831m	5.565ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	5.019m	4.150ms	2	10	20.00
V3		TOTAL			2	10	20.00
		TOTAL			870	890	97.75

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	19	76.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.20	97.89	92.58	99.89	76.76	95.53	98.89	97.88

Failure Buckets

Job kmac_masked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 6 failures:
- Test kmac_long_msg_and_output has 6 failures.
  - 1.kmac_long_msg_and_output.108738547817257000742452921490461579470392726243082281829681817700820415314633
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:ae3130c8-63d1-41b4-b6a0-f24e0d94b541
```
  - 2.kmac_long_msg_and_output.22176459080743634904401268676655735847571545244080657055806909984363081626261
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:11f5cfd6-38e0-423c-a147-f597ffecd4a0
```
  - ... and 4 more failures.
UVM_ERROR (kmac_scoreboard.sv:1188) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 5 failures:
- Test kmac_stress_all_with_rand_reset has 5 failures.
  - 0.kmac_stress_all_with_rand_reset.749420782047383532707270204453487273625426837807196981499626402705983579005
    Line 901, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4150129988 ps: (kmac_scoreboard.sv:1188) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483760 [0x80000070]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 4150129988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.kmac_stress_all_with_rand_reset.89145765661823790887683259769737185805451905239933934354504610114801847750303
    Line 469, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5735550509 ps: (kmac_scoreboard.sv:1188) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483752 [0x80000068]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 5735550509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

UVM_FATAL (kmac_scoreboard.sv:1638) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 3 failures:

Test kmac_app_with_partial_data has 1 failures.

0.kmac_app_with_partial_data.6897602508663185132526733190084481670808861256165759115116036946418889507624
Line 517, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_app_with_partial_data/latest/run.log

  UVM_FATAL @ 11100971494 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (202 [0xca] vs 139 [0x8b]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 11100971494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app has 1 failures.

7.kmac_app.48522724828579111168903894885669521756107367269584380059222155349609628954501
Line 859, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_app/latest/run.log

  UVM_FATAL @ 4319336032 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (219 [0xdb] vs 137 [0x89]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 4319336032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 1 failures.

26.kmac_entropy_refresh.167062702752621243656910356035720497831047750015564180893512131348466034039
Line 349, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/26.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 1570586716 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (27 [0x1b] vs 158 [0x9e]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 1570586716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:867) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
- Test kmac_stress_all_with_rand_reset has 3 failures.
  - 1.kmac_stress_all_with_rand_reset.73469176483839009668992784865769013403324276053349421618111181777334144643105
    Line 606, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3020719751 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3020719751 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.kmac_stress_all_with_rand_reset.67505882548316694856079278778274662985882345997167598834645332690983108580596
    Line 572, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3253558605 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3253558605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 2 failures:
- Test kmac_error has 1 failures.
  - 4.kmac_error.75194170199466980019995537524531580430226334558318273389924887855630592490005
    Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_error/latest/run.log
```
  UVM_ERROR @  87577792 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  87577792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_stress_all has 1 failures.
  - 27.kmac_stress_all.11870621801214644120956188931317852788170260104533571361681085659789052428006
    Line 607, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/27.kmac_stress_all/latest/run.log
```
  UVM_ERROR @ 8498752788 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 8498752788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_error has 1 failures.
  - 5.kmac_error.56103965258646144699128489378376863311183139828848040902340600782579778782757
    Line 1192, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_error/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```