KMAC/MASKED Simulation Results

Monday August 19 2024 23:02:17 UTC

GitHub Revision: `e45ccd274a`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 28901767565311589526059483176077826609560752276120463932311122284088110669824

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.480m	7.650ms	49	50	98.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.110s	27.873us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.220s	55.653us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	23.300s	25.024ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.360s	503.930us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.560s	96.572us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.220s	55.653us	20	20	100.00
		kmac_csr_aliasing	9.360s	503.930us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.790s	29.418us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.520s	80.212us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	long_msg_and_output	kmac_long_msg_and_output	1.481h	78.922ms	43	50	86.00
V2	burst_write	kmac_burst_write	28.374m	153.570ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	1.025h	290.162ms	5	5	100.00
		kmac_test_vectors_sha3_256	51.787m	74.880ms	5	5	100.00
		kmac_test_vectors_sha3_384	38.869m	912.150ms	5	5	100.00
		kmac_test_vectors_sha3_512	30.742m	48.093ms	5	5	100.00
		kmac_test_vectors_shake_128	1.327h	442.245ms	5	5	100.00
		kmac_test_vectors_shake_256	35.837m	74.579ms	5	5	100.00
		kmac_test_vectors_kmac	3.270s	176.646us	5	5	100.00
		kmac_test_vectors_kmac_xof	3.930s	780.715us	5	5	100.00
V2	sideload	kmac_sideload	9.910m	40.650ms	50	50	100.00
V2	app	kmac_app	8.406m	37.652ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	8.008m	16.145ms	9	10	90.00
V2	entropy_refresh	kmac_entropy_refresh	7.773m	37.995ms	50	50	100.00
V2	error	kmac_error	9.433m	78.334ms	50	50	100.00
V2	key_error	kmac_key_error	14.500s	4.336ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	46.680s	1.614ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	51.730s	9.839ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.232m	31.256ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	22.770s	3.715ms	50	50	100.00
V2	stress_all	kmac_stress_all	50.130m	253.610ms	49	50	98.00
V2	intr_test	kmac_intr_test	0.900s	189.436us	50	50	100.00
V2	alert_test	kmac_alert_test	0.940s	90.342us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.570s	143.377us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.570s	143.377us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.110s	27.873us	5	5	100.00
		kmac_csr_rw	1.220s	55.653us	20	20	100.00
		kmac_csr_aliasing	9.360s	503.930us	5	5	100.00
		kmac_same_csr_outstanding	2.580s	549.286us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.110s	27.873us	5	5	100.00
		kmac_csr_rw	1.220s	55.653us	20	20	100.00
		kmac_csr_aliasing	9.360s	503.930us	5	5	100.00
		kmac_same_csr_outstanding	2.580s	549.286us	20	20	100.00
V2		TOTAL			679	690	98.41
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.460s	82.533us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.460s	82.533us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.460s	82.533us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.460s	82.533us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.930s	129.167us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	2.008m	17.309ms	5	5	100.00
		kmac_tl_intg_err	5.730s	2.447ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.730s	2.447ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	22.770s	3.715ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.480m	7.650ms	49	50	98.00
V2S	sec_cm_key_sideload	kmac_sideload	9.910m	40.650ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.460s	82.533us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	2.008m	17.309ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	2.008m	17.309ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	2.008m	17.309ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.480m	7.650ms	49	50	98.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	22.770s	3.715ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	2.008m	17.309ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	7.967m	97.664ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.480m	7.650ms	49	50	98.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.944m	39.045ms	1	10	10.00
V3		TOTAL			1	10	10.00
		TOTAL			869	890	97.64

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	25	25	20	80.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.40	97.89	92.58	99.89	78.17	95.53	98.89	97.88

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 7 failures:
- Test kmac_stress_all_with_rand_reset has 7 failures.
  - 0.kmac_stress_all_with_rand_reset.115161335868307467328417414359696974589458827814695846265690349450748912963127
    Line 285, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1116173708 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1116173708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.112350299338867490686786315510408209210367355499116560356065887336729655737430
    Line 306, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 803062208 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 803062208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
Job kmac_masked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 7 failures:
- Test kmac_long_msg_and_output has 7 failures.
  - 15.kmac_long_msg_and_output.24414986574258592786568233697471828112883183531535183205479168494694185385484
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/15.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:6b66596c-98da-4098-bfad-874c53b4bade
```
  - 18.kmac_long_msg_and_output.69970686738849615873800824460205894921423785150998545849547611971260683195846
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/18.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:254800c3-a1ed-4ff3-83ac-0755c0c43b4a
```
  - ... and 5 more failures.

UVM_FATAL (kmac_scoreboard.sv:1638) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 3 failures:

Test kmac_app_with_partial_data has 1 failures.

5.kmac_app_with_partial_data.55195651685688727950723002652938083387679048707312864208071763071759010119860
Line 559, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_app_with_partial_data/latest/run.log

  UVM_FATAL @ 36516889362 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (13 [0xd] vs 158 [0x9e]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 36516889362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app has 1 failures.

24.kmac_app.62056497700177833999224413248787113207765894432449146772541656467609824154860
Line 283, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/24.kmac_app/latest/run.log

  UVM_FATAL @ 649953995 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (232 [0xe8] vs 46 [0x2e]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 649953995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 1 failures.

31.kmac_stress_all.34409080203890451724685917144484883561511609550990715835173461182066991270357
Line 407, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/31.kmac_stress_all/latest/run.log

  UVM_FATAL @ 12431819066 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (158 [0x9e] vs 147 [0x93]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 12431819066 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (kmac_scoreboard.sv:1188) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 2 failures:
- Test kmac_stress_all_with_rand_reset has 2 failures.
  - 6.kmac_stress_all_with_rand_reset.102485078247496405344065079197211686856721737142797625189783278463971828024904
    Line 301, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2040242685 ps: (kmac_scoreboard.sv:1188) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483768 [0x80000078]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 2040242685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.kmac_stress_all_with_rand_reset.54222303029480041958525890082476291074444044103443439250953174575722598617859
    Line 393, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4770936595 ps: (kmac_scoreboard.sv:1188) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483656 [0x80000008]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 4770936595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 1 failures:
- Test kmac_smoke has 1 failures.
  - 14.kmac_smoke.105287998778537676481534269431795028427450156236261541770247909499820527143874
    Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_smoke/latest/run.log
```
  UVM_ERROR @  44329064 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  44329064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_burst_write has 1 failures.
  - 37.kmac_burst_write.6098082402555601281054365521121905739631357552213697574861963337235750167782
    Line 1316, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/37.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```