KMAC/MASKED Simulation Results

Wednesday August 21 2024 01:12:47 UTC

GitHub Revision: `34b8fc33e3`

Branch: earlgrey_1_0_0_2024_08_20_RC0

Simulator: VCS

Build randomization enabled with --build-seed 77645589415139663032322841827996135987237190720163469870959218015679941996572

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	2.193m	4.486ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.850s	73.199us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.850s	395.281us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	31.230s	1.506ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	14.080s	1.881ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.620s	316.802us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.850s	395.281us	20	20	100.00
		kmac_csr_aliasing	14.080s	1.881ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	1.210s	20.138us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.490s	200.096us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	1.441h	271.526ms	50	50	100.00
V2	burst_write	kmac_burst_write	29.320m	28.001ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	56.549m	671.951ms	5	5	100.00
		kmac_test_vectors_sha3_256	41.543m	117.113ms	5	5	100.00
		kmac_test_vectors_sha3_384	30.911m	257.080ms	5	5	100.00
		kmac_test_vectors_sha3_512	23.467m	63.585ms	5	5	100.00
		kmac_test_vectors_shake_128	1.102h	838.734ms	5	5	100.00
		kmac_test_vectors_shake_256	48.918m	173.713ms	5	5	100.00
		kmac_test_vectors_kmac	4.990s	393.455us	5	5	100.00
		kmac_test_vectors_kmac_xof	4.880s	102.525us	5	5	100.00
V2	sideload	kmac_sideload	10.245m	31.105ms	50	50	100.00
V2	app	kmac_app	8.556m	142.596ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	7.644m	92.760ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	8.639m	18.289ms	50	50	100.00
V2	error	kmac_error	12.872m	146.484ms	50	50	100.00
V2	key_error	kmac_key_error	28.200s	12.239ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	1.314m	17.902ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	18.020s	369.379us	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.968m	35.905ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	1.010m	709.849us	50	50	100.00
V2	stress_all	kmac_stress_all	57.484m	162.794ms	48	50	96.00
V2	intr_test	kmac_intr_test	1.300s	19.121us	50	50	100.00
V2	alert_test	kmac_alert_test	1.410s	121.861us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	6.790s	2.252ms	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	6.790s	2.252ms	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.850s	73.199us	5	5	100.00
		kmac_csr_rw	1.850s	395.281us	20	20	100.00
		kmac_csr_aliasing	14.080s	1.881ms	5	5	100.00
		kmac_same_csr_outstanding	3.720s	199.996us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.850s	73.199us	5	5	100.00
		kmac_csr_rw	1.850s	395.281us	20	20	100.00
		kmac_csr_aliasing	14.080s	1.881ms	5	5	100.00
		kmac_same_csr_outstanding	3.720s	199.996us	20	20	100.00
V2		TOTAL			688	690	99.71
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.210s	568.808us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.210s	568.808us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.210s	568.808us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.210s	568.808us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	4.340s	510.856us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	2.900m	31.049ms	5	5	100.00
		kmac_tl_intg_err	8.500s	386.465us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	8.500s	386.465us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.010m	709.849us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	2.193m	4.486ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	10.245m	31.105ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.210s	568.808us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	2.900m	31.049ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	2.900m	31.049ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	2.900m	31.049ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	2.193m	4.486ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.010m	709.849us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	2.900m	31.049ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	7.570m	18.289ms	9	10	90.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	2.193m	4.486ms	50	50	100.00
V2S		TOTAL			74	75	98.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	7.990m	5.073ms	3	10	30.00
V3		TOTAL			3	10	30.00
		TOTAL			880	890	98.88

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	24	96.00
V2S	5	5	4	80.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.28	97.89	92.55	99.89	77.46	95.53	98.89	97.73

Failure Buckets

UVM_ERROR (kmac_scoreboard.sv:1188) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 5 failures:
- Test kmac_stress_all_with_rand_reset has 5 failures.
  - 0.kmac_stress_all_with_rand_reset.104778390761541978496054146974311784023654191038398974995426700001988290896141
    Line 173, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 24940297110 ps: (kmac_scoreboard.sv:1188) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483728 [0x80000050]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 24940297110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.kmac_stress_all_with_rand_reset.114340755145487356301090232899311447177608510384738267152097851288196484657669
    Line 188, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 926685876 ps: (kmac_scoreboard.sv:1188) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483664 [0x80000010]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 926685876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

UVM_FATAL (kmac_scoreboard.sv:1638) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 3 failures:

Test kmac_mubi has 1 failures.

7.kmac_mubi.50639410363638397077290691479417504711168121739956338520890499586583458369010
Line 178, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/7.kmac_mubi/latest/run.log

  UVM_FATAL @ 1585242504 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (95 [0x5f] vs 139 [0x8b]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 1585242504 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 2 failures.

9.kmac_stress_all.98120332451477339828374899641920988540670357569605949270309019018860430255735
Line 310, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/9.kmac_stress_all/latest/run.log

  UVM_FATAL @ 2971221129 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (232 [0xe8] vs 61 [0x3d]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 2971221129 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

47.kmac_stress_all.15421625103395836525790525460653686992421475172253863009249304662018813949273
Line 868, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/47.kmac_stress_all/latest/run.log

  UVM_FATAL @ 257824457733 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (255 [0xff] vs 61 [0x3d]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 257824457733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:867) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test kmac_stress_all_with_rand_reset has 2 failures.
  - 1.kmac_stress_all_with_rand_reset.109812852338569914107929563326518334167278685047309837098640198874741994066218
    Line 73, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4769607845 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 4769607845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.kmac_stress_all_with_rand_reset.71729565523181375315771216418821761128642010161619331438630234166423157602945
    Line 71, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 107296635 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 107296635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```