KMAC/MASKED Simulation Results

Saturday August 24 2024 20:58:08 UTC

GitHub Revision: e733a8ef8a

Branch: os_regression_2024_08_24

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 36240513409906943553650221581975102764006655953510936167454320581301243659163

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke kmac_smoke 2.544m 15.768ms 50 50 100.00
V1 csr_hw_reset kmac_csr_hw_reset 1.560s 80.096us 5 5 100.00
V1 csr_rw kmac_csr_rw 1.860s 217.340us 20 20 100.00
V1 csr_bit_bash kmac_csr_bit_bash 40.470s 14.455ms 5 5 100.00
V1 csr_aliasing kmac_csr_aliasing 10.830s 1.349ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset kmac_csr_mem_rw_with_rand_reset 3.990s 169.690us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr kmac_csr_rw 1.860s 217.340us 20 20 100.00
kmac_csr_aliasing 10.830s 1.349ms 5 5 100.00
V1 mem_walk kmac_mem_walk 1.140s 13.655us 5 5 100.00
V1 mem_partial_access kmac_mem_partial_access 2.240s 162.054us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 long_msg_and_output kmac_long_msg_and_output 1.793h 458.600ms 50 50 100.00
V2 burst_write kmac_burst_write 39.426m 430.557ms 50 50 100.00
V2 test_vectors kmac_test_vectors_sha3_224 57.365m 63.919ms 5 5 100.00
kmac_test_vectors_sha3_256 1.107h 332.746ms 5 5 100.00
kmac_test_vectors_sha3_384 47.774m 947.132ms 5 5 100.00
kmac_test_vectors_sha3_512 35.101m 95.423ms 5 5 100.00
kmac_test_vectors_shake_128 1.116h 73.158ms 5 5 100.00
kmac_test_vectors_shake_256 1.010h 87.182ms 5 5 100.00
kmac_test_vectors_kmac 6.140s 334.228us 5 5 100.00
kmac_test_vectors_kmac_xof 5.090s 659.079us 5 5 100.00
V2 sideload kmac_sideload 13.325m 21.797ms 50 50 100.00
V2 app kmac_app 12.594m 41.211ms 50 50 100.00
V2 app_with_partial_data kmac_app_with_partial_data 8.538m 9.564ms 10 10 100.00
V2 entropy_refresh kmac_entropy_refresh 10.211m 19.598ms 49 50 98.00
V2 error kmac_error 13.444m 136.402ms 49 50 98.00
V2 key_error kmac_key_error 22.950s 1.752ms 50 50 100.00
V2 edn_timeout_error kmac_edn_timeout_error 50.850s 804.493us 20 20 100.00
V2 entropy_mode_error kmac_entropy_mode_error 45.630s 478.302us 20 20 100.00
V2 entropy_ready_error kmac_entropy_ready_error 1.391m 2.600ms 10 10 100.00
V2 lc_escalation kmac_lc_escalation 1.052m 9.818ms 50 50 100.00
V2 stress_all kmac_stress_all 1.054h 252.999ms 48 50 96.00
V2 intr_test kmac_intr_test 1.320s 23.448us 50 50 100.00
V2 alert_test kmac_alert_test 1.450s 32.936us 50 50 100.00
V2 tl_d_oob_addr_access kmac_tl_errors 5.940s 179.723us 20 20 100.00
V2 tl_d_illegal_access kmac_tl_errors 5.940s 179.723us 20 20 100.00
V2 tl_d_outstanding_access kmac_csr_hw_reset 1.560s 80.096us 5 5 100.00
kmac_csr_rw 1.860s 217.340us 20 20 100.00
kmac_csr_aliasing 10.830s 1.349ms 5 5 100.00
kmac_same_csr_outstanding 3.920s 365.253us 20 20 100.00
V2 tl_d_partial_access kmac_csr_hw_reset 1.560s 80.096us 5 5 100.00
kmac_csr_rw 1.860s 217.340us 20 20 100.00
kmac_csr_aliasing 10.830s 1.349ms 5 5 100.00
kmac_same_csr_outstanding 3.920s 365.253us 20 20 100.00
V2 TOTAL 686 690 99.42
V2S shadow_reg_update_error kmac_shadow_reg_errors 2.120s 45.795us 20 20 100.00
V2S shadow_reg_read_clear_staged_value kmac_shadow_reg_errors 2.120s 45.795us 20 20 100.00
V2S shadow_reg_storage_error kmac_shadow_reg_errors 2.120s 45.795us 20 20 100.00
V2S shadowed_reset_glitch kmac_shadow_reg_errors 2.120s 45.795us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw kmac_shadow_reg_errors_with_csr_rw 4.300s 287.055us 20 20 100.00
V2S tl_intg_err kmac_sec_cm 2.650m 19.062ms 5 5 100.00
kmac_tl_intg_err 6.860s 806.660us 20 20 100.00
V2S sec_cm_bus_integrity kmac_tl_intg_err 6.860s 806.660us 20 20 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi kmac_lc_escalation 1.052m 9.818ms 50 50 100.00
V2S sec_cm_sw_key_key_masking kmac_smoke 2.544m 15.768ms 50 50 100.00
V2S sec_cm_key_sideload kmac_sideload 13.325m 21.797ms 50 50 100.00
V2S sec_cm_cfg_shadowed_config_shadow kmac_shadow_reg_errors 2.120s 45.795us 20 20 100.00
V2S sec_cm_fsm_sparse kmac_sec_cm 2.650m 19.062ms 5 5 100.00
V2S sec_cm_ctr_redun kmac_sec_cm 2.650m 19.062ms 5 5 100.00
V2S sec_cm_packer_ctr_redun kmac_sec_cm 2.650m 19.062ms 5 5 100.00
V2S sec_cm_cfg_shadowed_config_regwen kmac_smoke 2.544m 15.768ms 50 50 100.00
V2S sec_cm_fsm_global_esc kmac_lc_escalation 1.052m 9.818ms 50 50 100.00
V2S sec_cm_fsm_local_esc kmac_sec_cm 2.650m 19.062ms 5 5 100.00
V2S sec_cm_absorbed_ctrl_mubi kmac_mubi 7.783m 9.583ms 10 10 100.00
V2S sec_cm_sw_cmd_ctrl_sparse kmac_smoke 2.544m 15.768ms 50 50 100.00
V2S TOTAL 75 75 100.00
V3 throughput kmac_throughput 0 0 --
V3 stress_all_with_rand_reset kmac_stress_all_with_rand_reset 3.749m 7.645ms 5 10 50.00
V3 TOTAL 5 10 50.00
TOTAL 881 890 98.99

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 25 25 22 88.00
V2S 5 5 5 100.00
V3 2 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
94.24 97.91 92.62 99.89 76.76 95.59 99.05 97.88

Failure Buckets

Past Results