KMAC/MASKED Simulation Results

Monday August 26 2024 23:33:20 UTC

GitHub Revision: `4674f625b3`

Branch: os_regression_2024_08_26

Simulator: VCS

Build randomization enabled with --build-seed 27137705585251537962012108482438895412147493342955425380690984800523869492310

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	2.276m	45.254ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.420s	41.559us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.590s	42.566us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	16.750s	1.014ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	8.950s	1.650ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.820s	726.234us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.590s	42.566us	20	20	100.00
		kmac_csr_aliasing	8.950s	1.650ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	1.050s	14.246us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.750s	179.710us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	1.391h	110.206ms	50	50	100.00
V2	burst_write	kmac_burst_write	24.639m	27.417ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	44.689m	91.112ms	5	5	100.00
		kmac_test_vectors_sha3_256	49.331m	61.408ms	5	5	100.00
		kmac_test_vectors_sha3_384	32.105m	177.296ms	5	5	100.00
		kmac_test_vectors_sha3_512	25.924m	166.825ms	5	5	100.00
		kmac_test_vectors_shake_128	47.902m	255.004ms	5	5	100.00
		kmac_test_vectors_shake_256	46.554m	344.790ms	5	5	100.00
		kmac_test_vectors_kmac	4.400s	104.134us	5	5	100.00
		kmac_test_vectors_kmac_xof	4.140s	734.674us	5	5	100.00
V2	sideload	kmac_sideload	12.050m	89.999ms	50	50	100.00
V2	app	kmac_app	8.285m	12.781ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	8.512m	29.787ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	8.483m	19.446ms	50	50	100.00
V2	error	kmac_error	8.239m	23.864ms	50	50	100.00
V2	key_error	kmac_key_error	22.650s	3.614ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	51.690s	1.894ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	51.910s	3.349ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.141m	8.805ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	57.180s	11.533ms	50	50	100.00
V2	stress_all	kmac_stress_all	54.913m	148.202ms	50	50	100.00
V2	intr_test	kmac_intr_test	1.140s	14.233us	50	50	100.00
V2	alert_test	kmac_alert_test	1.360s	22.163us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.570s	61.093us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.570s	61.093us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.420s	41.559us	5	5	100.00
		kmac_csr_rw	1.590s	42.566us	20	20	100.00
		kmac_csr_aliasing	8.950s	1.650ms	5	5	100.00
		kmac_same_csr_outstanding	2.490s	361.728us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.420s	41.559us	5	5	100.00
		kmac_csr_rw	1.590s	42.566us	20	20	100.00
		kmac_csr_aliasing	8.950s	1.650ms	5	5	100.00
		kmac_same_csr_outstanding	2.490s	361.728us	20	20	100.00
V2		TOTAL			689	690	99.86
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.650s	42.751us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.650s	42.751us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.650s	42.751us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.650s	42.751us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.210s	457.006us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	2.950m	9.801ms	5	5	100.00
		kmac_tl_intg_err	5.000s	510.959us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.000s	510.959us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	57.180s	11.533ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	2.276m	45.254ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	12.050m	89.999ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.650s	42.751us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	2.950m	9.801ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	2.950m	9.801ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	2.950m	9.801ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	2.276m	45.254ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	57.180s	11.533ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	2.950m	9.801ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	8.538m	69.743ms	7	10	70.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	2.276m	45.254ms	50	50	100.00
V2S		TOTAL			72	75	96.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	3.785m	16.134ms	1	10	10.00
V3		TOTAL			1	10	10.00
		TOTAL			877	890	98.54

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	24	96.00
V2S	5	5	4	80.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.10	97.89	92.55	99.89	76.06	95.53	98.89	97.88

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 5 failures:
- Test kmac_stress_all_with_rand_reset has 5 failures.
  - 0.kmac_stress_all_with_rand_reset.110821874559463478975820586948811305084668897617639648313739432811285821859347
    Line 290, in log /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2366014384 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2366014384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.6442449680984057773212177364322002574667013575708592238414601513596132171039
    Line 252, in log /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8070176976 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 8070176976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

UVM_FATAL (kmac_scoreboard.sv:1638) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 4 failures:

Test kmac_mubi has 3 failures.

2.kmac_mubi.35231741526337024530576263461083927902011999408154303379202531862439254637186
Line 220, in log /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/2.kmac_mubi/latest/run.log

  UVM_FATAL @ 1014685123 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (223 [0xdf] vs 35 [0x23]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 1014685123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.kmac_mubi.95447557476775588777259967905051197010575041645731491136911029779147692977046
Line 424, in log /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/3.kmac_mubi/latest/run.log

  UVM_FATAL @ 4956175595 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (110 [0x6e] vs 130 [0x82]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 4956175595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test kmac_app has 1 failures.

44.kmac_app.114503204030090415301430002804231116091252535049189564047071873506003506231537
Line 246, in log /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/44.kmac_app/latest/run.log

  UVM_FATAL @ 16491962883 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (237 [0xed] vs 34 [0x22]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 16491962883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (kmac_scoreboard.sv:1188) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 4 failures:
- Test kmac_stress_all_with_rand_reset has 4 failures.
  - 2.kmac_stress_all_with_rand_reset.91388732594152967563138751512635109408175343790897196408539965667110563153355
    Line 418, in log /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2521070452 ps: (kmac_scoreboard.sv:1188) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483688 [0x80000028]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 2521070452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.kmac_stress_all_with_rand_reset.52482474580540942302559537447946867891849982278453924467158661845429107001879
    Line 115, in log /workspaces/repo/scratch/os_regression_2024_08_26/kmac_masked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 343217931 ps: (kmac_scoreboard.sv:1188) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483680 [0x80000020]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 343217931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.