KMAC/MASKED Simulation Results

Wednesday August 28 2024 16:26:26 UTC

GitHub Revision: `a861deb3de`

Branch: os_regression_2024_08_28

Simulator: VCS

Build randomization enabled with --build-seed 1071354200461384473511155521960728188378582408849032283874664554749864050652

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.773m	15.102ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.900s	104.760us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.850s	30.063us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	39.170s	7.602ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	8.040s	268.156us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.990s	173.347us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.850s	30.063us	20	20	100.00
		kmac_csr_aliasing	8.040s	268.156us	5	5	100.00
V1	mem_walk	kmac_mem_walk	1.240s	14.399us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.300s	68.136us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	1.601h	130.760ms	50	50	100.00
V2	burst_write	kmac_burst_write	31.526m	40.759ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	54.034m	90.739ms	5	5	100.00
		kmac_test_vectors_sha3_256	43.404m	123.839ms	5	5	100.00
		kmac_test_vectors_sha3_384	27.889m	50.982ms	5	5	100.00
		kmac_test_vectors_sha3_512	25.874m	367.857ms	5	5	100.00
		kmac_test_vectors_shake_128	44.454m	21.522ms	5	5	100.00
		kmac_test_vectors_shake_256	45.059m	76.387ms	5	5	100.00
		kmac_test_vectors_kmac	3.480s	78.704us	5	5	100.00
		kmac_test_vectors_kmac_xof	4.230s	597.856us	5	5	100.00
V2	sideload	kmac_sideload	11.531m	92.331ms	50	50	100.00
V2	app	kmac_app	8.638m	77.634ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	8.177m	20.483ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	8.362m	8.793ms	49	50	98.00
V2	error	kmac_error	10.221m	18.844ms	49	50	98.00
V2	key_error	kmac_key_error	23.550s	17.969ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	51.760s	1.464ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	49.370s	3.868ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.619m	6.859ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	33.820s	1.661ms	50	50	100.00
V2	stress_all	kmac_stress_all	1.437h	272.525ms	48	50	96.00
V2	intr_test	kmac_intr_test	1.350s	17.617us	50	50	100.00
V2	alert_test	kmac_alert_test	1.460s	171.735us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	6.810s	166.767us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	6.810s	166.767us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.900s	104.760us	5	5	100.00
		kmac_csr_rw	1.850s	30.063us	20	20	100.00
		kmac_csr_aliasing	8.040s	268.156us	5	5	100.00
		kmac_same_csr_outstanding	3.920s	98.422us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.900s	104.760us	5	5	100.00
		kmac_csr_rw	1.850s	30.063us	20	20	100.00
		kmac_csr_aliasing	8.040s	268.156us	5	5	100.00
		kmac_same_csr_outstanding	3.920s	98.422us	20	20	100.00
V2		TOTAL			686	690	99.42
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.480s	797.084us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.480s	797.084us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.480s	797.084us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.480s	797.084us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	4.840s	533.183us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.937m	6.756ms	5	5	100.00
		kmac_tl_intg_err	7.010s	451.618us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	7.010s	451.618us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	33.820s	1.661ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.773m	15.102ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	11.531m	92.331ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.480s	797.084us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.937m	6.756ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.937m	6.756ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.937m	6.756ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.773m	15.102ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	33.820s	1.661ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.937m	6.756ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	9.868m	19.106ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.773m	15.102ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	3.355m	13.887ms	3	10	30.00
V3		TOTAL			3	10	30.00
		TOTAL			879	890	98.76

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	22	88.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.28	97.89	92.55	99.89	77.46	95.53	98.89	97.73

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 4 failures:
- Test kmac_stress_all_with_rand_reset has 4 failures.
  - 0.kmac_stress_all_with_rand_reset.23550596834291958314500701964296274201809603354919934624493619229864530060490
    Line 85, in log /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 737591492 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 737591492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.48839908566880016705814559876787088607163003349317711706893985889242586799383
    Line 149, in log /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5506345080 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 5506345080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 3 failures:

Test kmac_error has 1 failures.

0.kmac_error.32659628033652232336156815520182831900589521555078727619467704265763976266065
Line 67, in log /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/0.kmac_error/latest/run.log

  UVM_ERROR @  60955986 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  60955986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 2 failures.

5.kmac_stress_all.66885887081574788827041127991712405430594536970241076562417573453183853677654
Line 1287, in log /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/5.kmac_stress_all/latest/run.log

  UVM_ERROR @ 31807826528 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 31807826528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

44.kmac_stress_all.39368908623760966196479042686901868243676992910348083030351980199049518551182
Line 1621, in log /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/44.kmac_stress_all/latest/run.log

  UVM_ERROR @ 90273113685 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 90273113685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (kmac_scoreboard.sv:1188) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 3 failures:
- Test kmac_stress_all_with_rand_reset has 3 failures.
  - 2.kmac_stress_all_with_rand_reset.95017632410837529085163430756621463033089475324495292635485371748831672252581
    Line 90, in log /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 488275584 ps: (kmac_scoreboard.sv:1188) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483680 [0x80000020]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 488275584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.kmac_stress_all_with_rand_reset.45159397480560541197425735927826180896497296457700799492964414741726446472245
    Line 76, in log /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 365094094 ps: (kmac_scoreboard.sv:1188) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483752 [0x80000068]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 365094094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (kmac_scoreboard.sv:1638) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 1 failures:
- Test kmac_entropy_refresh has 1 failures.
  - 45.kmac_entropy_refresh.42438811460014863289008491895928834919341809947642468401868870113270646347564
    Line 772, in log /workspaces/repo/scratch/os_regression_2024_08_28/kmac_masked-sim-vcs/45.kmac_entropy_refresh/latest/run.log
```
  UVM_FATAL @ 18448692889 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (95 [0x5f] vs 63 [0x3f]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 18448692889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```