KMAC/MASKED Simulation Results

Sunday September 01 2024 02:56:32 UTC

GitHub Revision: `ed1c41cd0f`

Branch: os_regression_2024_08_31

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 79046303479535931055412478968949166876277637335647713094117953182855865639399

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	2.245m	57.220ms	49	50	98.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.760s	114.542us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.870s	76.232us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	30.050s	1.317ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	13.260s	2.113ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	4.020s	339.483us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.870s	76.232us	20	20	100.00
		kmac_csr_aliasing	13.260s	2.113ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	1.170s	28.023us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.230s	68.334us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	long_msg_and_output	kmac_long_msg_and_output	1.697h	494.492ms	50	50	100.00
V2	burst_write	kmac_burst_write	30.508m	96.870ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	51.888m	96.276ms	5	5	100.00
		kmac_test_vectors_sha3_256	47.749m	88.206ms	5	5	100.00
		kmac_test_vectors_sha3_384	45.290s	7.839ms	5	5	100.00
		kmac_test_vectors_sha3_512	25.589m	270.775ms	5	5	100.00
		kmac_test_vectors_shake_128	1.019h	144.916ms	4	5	80.00
		kmac_test_vectors_shake_256	43.356m	60.402ms	5	5	100.00
		kmac_test_vectors_kmac	5.840s	264.554us	5	5	100.00
		kmac_test_vectors_kmac_xof	3.250s	56.357us	5	5	100.00
V2	sideload	kmac_sideload	11.593m	83.405ms	50	50	100.00
V2	app	kmac_app	7.684m	76.873ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.933m	37.960ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	8.902m	90.486ms	50	50	100.00
V2	error	kmac_error	11.035m	66.199ms	50	50	100.00
V2	key_error	kmac_key_error	25.600s	7.789ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	45.840s	4.645ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	44.990s	1.341ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.825m	60.641ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	39.010s	3.693ms	50	50	100.00
V2	stress_all	kmac_stress_all	42.647m	49.646ms	49	50	98.00
V2	intr_test	kmac_intr_test	1.320s	26.644us	50	50	100.00
V2	alert_test	kmac_alert_test	1.400s	165.625us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	6.230s	684.056us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	6.230s	684.056us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.760s	114.542us	5	5	100.00
		kmac_csr_rw	1.870s	76.232us	20	20	100.00
		kmac_csr_aliasing	13.260s	2.113ms	5	5	100.00
		kmac_same_csr_outstanding	4.360s	404.715us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.760s	114.542us	5	5	100.00
		kmac_csr_rw	1.870s	76.232us	20	20	100.00
		kmac_csr_aliasing	13.260s	2.113ms	5	5	100.00
		kmac_same_csr_outstanding	4.360s	404.715us	20	20	100.00
V2		TOTAL			687	690	99.57
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.100s	45.104us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.100s	45.104us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.100s	45.104us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.100s	45.104us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	4.850s	319.388us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	2.187m	7.024ms	5	5	100.00
		kmac_tl_intg_err	8.080s	261.286us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	8.080s	261.286us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	39.010s	3.693ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	2.245m	57.220ms	49	50	98.00
V2S	sec_cm_key_sideload	kmac_sideload	11.593m	83.405ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.100s	45.104us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	2.187m	7.024ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	2.187m	7.024ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	2.187m	7.024ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	2.245m	57.220ms	49	50	98.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	39.010s	3.693ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	2.187m	7.024ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	9.605m	77.052ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	2.245m	57.220ms	49	50	98.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	6.095m	45.814ms	4	10	40.00
V3		TOTAL			4	10	40.00
		TOTAL			880	890	98.88

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	25	25	22	88.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.14	97.91	92.62	99.89	76.06	95.59	99.05	97.88

Failure Buckets

UVM_ERROR (kmac_scoreboard.sv:1196) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 6 failures:
- Test kmac_stress_all_with_rand_reset has 6 failures.
  - 2.kmac_stress_all_with_rand_reset.12290038176508978758070210863557383572325579891119440504209540572171581315133
    Line 110, in log /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 924757479 ps: (kmac_scoreboard.sv:1196) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483648 [0x80000000]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 924757479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.kmac_stress_all_with_rand_reset.35077181283320914176982429079582593614161611440932515241682284132858163677927
    Line 609, in log /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 15114486697 ps: (kmac_scoreboard.sv:1196) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483656 [0x80000008]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 15114486697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 3 failures:
- Test kmac_test_vectors_shake_128 has 1 failures.
  - 1.kmac_test_vectors_shake_128.63200031893998000817435575007632972874799850237192061881663971121988621028145
    Line 66, in log /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/1.kmac_test_vectors_shake_128/latest/run.log
```
  UVM_ERROR @  24865949 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  24865949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_smoke has 1 failures.
  - 11.kmac_smoke.62085282838805259801751737722268252675523080621247845603662192260766444839166
    Line 67, in log /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/11.kmac_smoke/latest/run.log
```
  UVM_ERROR @  70933178 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  70933178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_stress_all has 1 failures.
  - 25.kmac_stress_all.18413409574238204737604218236565570569690472777771141413180440735528769779298
    Line 68, in log /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/25.kmac_stress_all/latest/run.log
```
  UVM_ERROR @  42584721 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  42584721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_burst_write has 1 failures.
  - 25.kmac_burst_write.107276955878291060317922655263414976121625502899352350610422107415387083463003
    Line 1165, in log /workspaces/repo/scratch/os_regression_2024_08_31/kmac_masked-sim-vcs/25.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

KMAC/MASKED Simulation Results

Sunday September 01 2024 02:56:32 UTC

GitHub Revision: ed1c41cd0f

Branch: os_regression_2024_08_31

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 79046303479535931055412478968949166876277637335647713094117953182855865639399

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `ed1c41cd0f`